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<a href="#nested-classes">Data Structures</a> &#124;
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<div class="title">Axipcie_v3_0</div>  </div>
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axi_pcie___config.html">XAxiPcie_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains IP hardware configuration information.  <a href="struct_x_axi_pcie___config.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> driver instance data.  <a href="struct_x_axi_pcie.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axi_pcie___bar_addr.html">XAxiPcie_BarAddr</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The user is required to use this strucuture when reading or writing translation vector between local bus BARs and AXI PCIe BARs.  <a href="struct_x_axi_pcie___bar_addr.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga7e5fb7cdef729030bf31e9c3651253b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga7e5fb7cdef729030bf31e9c3651253b1">XAXIPCIE_VSEC1</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:ga7e5fb7cdef729030bf31e9c3651253b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">First VSEC Register.  <a href="#ga7e5fb7cdef729030bf31e9c3651253b1">More...</a><br /></td></tr>
<tr class="separator:ga7e5fb7cdef729030bf31e9c3651253b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga08b7198f8d99e2f00b912ae94f25d088"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga08b7198f8d99e2f00b912ae94f25d088">XAXIPCIE_VSEC2</a>&#160;&#160;&#160;0x01</td></tr>
<tr class="memdesc:ga08b7198f8d99e2f00b912ae94f25d088"><td class="mdescLeft">&#160;</td><td class="mdescRight">Second VSEC Register.  <a href="#ga08b7198f8d99e2f00b912ae94f25d088">More...</a><br /></td></tr>
<tr class="separator:ga08b7198f8d99e2f00b912ae94f25d088"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga08e3f639ed3ca042d429630fec260654"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga08e3f639ed3ca042d429630fec260654">XAxiPcie_IsLinkUp</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga08e3f639ed3ca042d429630fec260654"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether link is up or not.  <a href="#ga08e3f639ed3ca042d429630fec260654">More...</a><br /></td></tr>
<tr class="separator:ga08e3f639ed3ca042d429630fec260654"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4eff130db70eebadac90b43cbd2561fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga4eff130db70eebadac90b43cbd2561fa">XAxiPcie_IsEcamBusy</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga4eff130db70eebadac90b43cbd2561fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether ECAM is busy or not.  <a href="#ga4eff130db70eebadac90b43cbd2561fa">More...</a><br /></td></tr>
<tr class="separator:ga4eff130db70eebadac90b43cbd2561fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5e38a3a5815c463c52461a8f7f52b75"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:gab5e38a3a5815c463c52461a8f7f52b75"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to read register.  <a href="#gab5e38a3a5815c463c52461a8f7f52b75">More...</a><br /></td></tr>
<tr class="separator:gab5e38a3a5815c463c52461a8f7f52b75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3312e39c24adeb6a06a7408a68a1e80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaf3312e39c24adeb6a06a7408a68a1e80">XAxiPcie_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="memdesc:gaf3312e39c24adeb6a06a7408a68a1e80"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to write register.  <a href="#gaf3312e39c24adeb6a06a7408a68a1e80">More...</a><br /></td></tr>
<tr class="separator:gaf3312e39c24adeb6a06a7408a68a1e80"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga911e4cd0c119271f6c01c9b1ac827df1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_axi_pcie___config.html">XAxiPcie_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga911e4cd0c119271f6c01c9b1ac827df1">XAxiPcie_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:ga911e4cd0c119271f6c01c9b1ac827df1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lookup the device configuration based on the unique device ID.  <a href="#ga911e4cd0c119271f6c01c9b1ac827df1">More...</a><br /></td></tr>
<tr class="separator:ga911e4cd0c119271f6c01c9b1ac827df1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6eaa13c68af6eb2ca12ae556f9e0769b"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga6eaa13c68af6eb2ca12ae556f9e0769b">XAxiPcie_CfgInitialize</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, <a class="el" href="struct_x_axi_pcie___config.html">XAxiPcie_Config</a> *CfgPtr, UINTPTR EffectiveAddress)</td></tr>
<tr class="memdesc:ga6eaa13c68af6eb2ca12ae556f9e0769b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance provided by the caller based on the given Config structure.  <a href="#ga6eaa13c68af6eb2ca12ae556f9e0769b">More...</a><br /></td></tr>
<tr class="separator:ga6eaa13c68af6eb2ca12ae556f9e0769b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga745d2811e366fbe0e5499cfef90adbcc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga745d2811e366fbe0e5499cfef90adbcc">XAxiPcie_GetVsecCapability</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u8 VsecNum, u16 *VsecIdPtr, u8 *VersionPtr, u16 *NextCapPtr)</td></tr>
<tr class="memdesc:ga745d2811e366fbe0e5499cfef90adbcc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API is used to read the VSEC Capability Register.  <a href="#ga745d2811e366fbe0e5499cfef90adbcc">More...</a><br /></td></tr>
<tr class="separator:ga745d2811e366fbe0e5499cfef90adbcc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa26f5255cb42e55351c7cb802f71d56c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaa26f5255cb42e55351c7cb802f71d56c">XAxiPcie_GetVsecHeader</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u8 VsecNum, u16 *VsecIdPtr, u8 *RevisionPtr, u16 *LengthPtr)</td></tr>
<tr class="memdesc:gaa26f5255cb42e55351c7cb802f71d56c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API is used to read the VSEC Header Register.  <a href="#gaa26f5255cb42e55351c7cb802f71d56c">More...</a><br /></td></tr>
<tr class="separator:gaa26f5255cb42e55351c7cb802f71d56c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga75ca6a068024666c0199ea90d3ce4276"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga75ca6a068024666c0199ea90d3ce4276">XAxiPcie_GetBridgeInfo</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u8 *Gen2Ptr, u8 *RootPortPtr, u8 *ECAMSizePtr)</td></tr>
<tr class="memdesc:ga75ca6a068024666c0199ea90d3ce4276"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API Reads the Bridge info register.  <a href="#ga75ca6a068024666c0199ea90d3ce4276">More...</a><br /></td></tr>
<tr class="separator:ga75ca6a068024666c0199ea90d3ce4276"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77063428b5641d07910419770813c148"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga77063428b5641d07910419770813c148">XAxiPcie_GetRequesterId</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u8 *BusNumPtr, u8 *DevNumPtr, u8 *FunNumPtr, u8 *PortNumPtr)</td></tr>
<tr class="memdesc:ga77063428b5641d07910419770813c148"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the Bus Location register.  <a href="#ga77063428b5641d07910419770813c148">More...</a><br /></td></tr>
<tr class="separator:ga77063428b5641d07910419770813c148"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga372301905fec6833c06320fb45261cd7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga372301905fec6833c06320fb45261cd7">XAxiPcie_GetPhyStatusCtrl</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u32 *PhyState)</td></tr>
<tr class="memdesc:ga372301905fec6833c06320fb45261cd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API is used to read the Phy Status/Control Register.  <a href="#ga372301905fec6833c06320fb45261cd7">More...</a><br /></td></tr>
<tr class="separator:ga372301905fec6833c06320fb45261cd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0899628f4ecfb6d3b05671933c375ae5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga0899628f4ecfb6d3b05671933c375ae5">XAxiPcie_GetRootPortStatusCtrl</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u32 *StatusPtr)</td></tr>
<tr class="memdesc:ga0899628f4ecfb6d3b05671933c375ae5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Root Port Status/Control Register.  <a href="#ga0899628f4ecfb6d3b05671933c375ae5">More...</a><br /></td></tr>
<tr class="separator:ga0899628f4ecfb6d3b05671933c375ae5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2860cd7b0180a99fb324c085fc8fa746"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga2860cd7b0180a99fb324c085fc8fa746">XAxiPcie_SetRootPortStatusCtrl</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u32 StatusData)</td></tr>
<tr class="memdesc:ga2860cd7b0180a99fb324c085fc8fa746"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write Value in Root Port Status/Control Register.  <a href="#ga2860cd7b0180a99fb324c085fc8fa746">More...</a><br /></td></tr>
<tr class="separator:ga2860cd7b0180a99fb324c085fc8fa746"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ce4f790929f629f225c2ef2fbcc2647"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga0ce4f790929f629f225c2ef2fbcc2647">XAxiPcie_SetRootPortMSIBase</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, unsigned long long MsiBase)</td></tr>
<tr class="memdesc:ga0ce4f790929f629f225c2ef2fbcc2647"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write MSI Base Address to Root Port MSI Base Address Register.  <a href="#ga0ce4f790929f629f225c2ef2fbcc2647">More...</a><br /></td></tr>
<tr class="separator:ga0ce4f790929f629f225c2ef2fbcc2647"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga32604cb99f7d35107ee59ff121e0024d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga32604cb99f7d35107ee59ff121e0024d">XAxiPcie_GetRootPortErrFIFOMsg</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u16 *ReqIdPtr, u8 *ErrType, u8 *ErrValid)</td></tr>
<tr class="memdesc:ga32604cb99f7d35107ee59ff121e0024d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Root Port Error FIFO Message.  <a href="#ga32604cb99f7d35107ee59ff121e0024d">More...</a><br /></td></tr>
<tr class="separator:ga32604cb99f7d35107ee59ff121e0024d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga225811fdbd9b22b8208a83ca4d3818ce"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga225811fdbd9b22b8208a83ca4d3818ce">XAxiPcie_ClearRootPortErrFIFOMsg</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga225811fdbd9b22b8208a83ca4d3818ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear Root Port Error FIFO Message.  <a href="#ga225811fdbd9b22b8208a83ca4d3818ce">More...</a><br /></td></tr>
<tr class="separator:ga225811fdbd9b22b8208a83ca4d3818ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b13520d9f4472bc16cfa5a6266f6795"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga8b13520d9f4472bc16cfa5a6266f6795">XAxiPcie_GetRootPortIntFIFOReg</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u16 *ReqIdPtr, u16 *MsiAddr, u8 *MsiInt, u8 *IntValid, u16 *MsiMsgData)</td></tr>
<tr class="memdesc:ga8b13520d9f4472bc16cfa5a6266f6795"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Root Port Interrupt FIFO message Register 1 &amp; 2.  <a href="#ga8b13520d9f4472bc16cfa5a6266f6795">More...</a><br /></td></tr>
<tr class="separator:ga8b13520d9f4472bc16cfa5a6266f6795"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4b043d41a5668f97f83518327023ea0d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga4b043d41a5668f97f83518327023ea0d">XAxiPcie_ClearRootPortIntFIFOReg</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga4b043d41a5668f97f83518327023ea0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear Root Port FIFO Interrupt message Register 1 &amp; 2.  <a href="#ga4b043d41a5668f97f83518327023ea0d">More...</a><br /></td></tr>
<tr class="separator:ga4b043d41a5668f97f83518327023ea0d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga19d8a1973231160bdd518b1c62bda3d4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga19d8a1973231160bdd518b1c62bda3d4">XAxiPcie_GetLocalBusBar2PcieBar</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u8 BarNumber, <a class="el" href="struct_x_axi_pcie___bar_addr.html">XAxiPcie_BarAddr</a> *BarAddrPtr)</td></tr>
<tr class="memdesc:ga19d8a1973231160bdd518b1c62bda3d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller.  <a href="#ga19d8a1973231160bdd518b1c62bda3d4">More...</a><br /></td></tr>
<tr class="separator:ga19d8a1973231160bdd518b1c62bda3d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga51ee29d03fbefc82b9208f46a12d5a06"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga51ee29d03fbefc82b9208f46a12d5a06">XAxiPcie_SetLocalBusBar2PcieBar</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u8 BarNumber, <a class="el" href="struct_x_axi_pcie___bar_addr.html">XAxiPcie_BarAddr</a> *BarAddrPtr)</td></tr>
<tr class="memdesc:ga51ee29d03fbefc82b9208f46a12d5a06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller.  <a href="#ga51ee29d03fbefc82b9208f46a12d5a06">More...</a><br /></td></tr>
<tr class="separator:ga51ee29d03fbefc82b9208f46a12d5a06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9494095b9350f455af9e7da5375d522"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gad9494095b9350f455af9e7da5375d522">XAxiPcie_ReadLocalConfigSpace</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u16 Offset, u32 *DataPtr)</td></tr>
<tr class="memdesc:gad9494095b9350f455af9e7da5375d522"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read 32-bit value from one of this IP own configuration space.  <a href="#gad9494095b9350f455af9e7da5375d522">More...</a><br /></td></tr>
<tr class="separator:gad9494095b9350f455af9e7da5375d522"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafbdf9a7e71effb96353079d1c177888b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gafbdf9a7e71effb96353079d1c177888b">XAxiPcie_WriteLocalConfigSpace</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u16 Offset, u32 Data)</td></tr>
<tr class="memdesc:gafbdf9a7e71effb96353079d1c177888b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write 32-bit value to one of this IP own configuration space.  <a href="#gafbdf9a7e71effb96353079d1c177888b">More...</a><br /></td></tr>
<tr class="separator:gafbdf9a7e71effb96353079d1c177888b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae4aafc6b1766352ed5347e40762f0649"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gae4aafc6b1766352ed5347e40762f0649">XAxiPcie_ReadRemoteConfigSpace</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u8 Bus, u8 Device, u8 Function, u16 Offset, u32 *DataPtr)</td></tr>
<tr class="memdesc:gae4aafc6b1766352ed5347e40762f0649"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read 32-bit value from external PCIe Function's configuration space.  <a href="#gae4aafc6b1766352ed5347e40762f0649">More...</a><br /></td></tr>
<tr class="separator:gae4aafc6b1766352ed5347e40762f0649"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb4d67df95f1c7b0010e370312283f22"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gadb4d67df95f1c7b0010e370312283f22">XAxiPcie_WriteRemoteConfigSpace</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u8 Bus, u8 Device, u8 Function, u16 Offset, u32 Data)</td></tr>
<tr class="memdesc:gadb4d67df95f1c7b0010e370312283f22"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write 32-bit value to external PCIe function's configuration space.  <a href="#gadb4d67df95f1c7b0010e370312283f22">More...</a><br /></td></tr>
<tr class="separator:gadb4d67df95f1c7b0010e370312283f22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga062809d176f81251886d5372c0714f7a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga062809d176f81251886d5372c0714f7a">XAxiPcie_EnableGlobalInterrupt</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga062809d176f81251886d5372c0714f7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the Global Interrupt.  <a href="#ga062809d176f81251886d5372c0714f7a">More...</a><br /></td></tr>
<tr class="separator:ga062809d176f81251886d5372c0714f7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaace3ba2f6c70cd207c9c65d92c634ee8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaace3ba2f6c70cd207c9c65d92c634ee8">XAxiPcie_DisableGlobalInterrupt</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaace3ba2f6c70cd207c9c65d92c634ee8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the Global Interrupt.  <a href="#gaace3ba2f6c70cd207c9c65d92c634ee8">More...</a><br /></td></tr>
<tr class="separator:gaace3ba2f6c70cd207c9c65d92c634ee8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22a95261655e78a944d1a2462031da57"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga22a95261655e78a944d1a2462031da57">XAxiPcie_EnableInterrupts</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u32 EnableMask)</td></tr>
<tr class="memdesc:ga22a95261655e78a944d1a2462031da57"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the IP interrupt bits passed into "EnableMask".  <a href="#ga22a95261655e78a944d1a2462031da57">More...</a><br /></td></tr>
<tr class="separator:ga22a95261655e78a944d1a2462031da57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae238cf115bd039e0f7228e385c893aad"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gae238cf115bd039e0f7228e385c893aad">XAxiPcie_DisableInterrupts</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u32 DisableMask)</td></tr>
<tr class="memdesc:gae238cf115bd039e0f7228e385c893aad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the IP interrupt bits passed into "DisableMask".  <a href="#gae238cf115bd039e0f7228e385c893aad">More...</a><br /></td></tr>
<tr class="separator:gae238cf115bd039e0f7228e385c893aad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae118e9d7fd6b78ca0b8d4fd6694f9808"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gae118e9d7fd6b78ca0b8d4fd6694f9808">XAxiPcie_GetEnabledInterrupts</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u32 *EnabledMaskPtr)</td></tr>
<tr class="memdesc:gae118e9d7fd6b78ca0b8d4fd6694f9808"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the currently enabled interrupt bits of the IP and pass them back to the caller into "EnabledMask".  <a href="#gae118e9d7fd6b78ca0b8d4fd6694f9808">More...</a><br /></td></tr>
<tr class="separator:gae118e9d7fd6b78ca0b8d4fd6694f9808"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec39c65db1aeac38798a250a25298208"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaec39c65db1aeac38798a250a25298208">XAxiPcie_GetPendingInterrupts</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u32 *PendingMaskPtr)</td></tr>
<tr class="memdesc:gaec39c65db1aeac38798a250a25298208"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the currently pending interrupt bits of the IP and pass them back to the caller into "PendingMask".  <a href="#gaec39c65db1aeac38798a250a25298208">More...</a><br /></td></tr>
<tr class="separator:gaec39c65db1aeac38798a250a25298208"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabdf66d0cb481a5eea62e1f98e71d9520"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gabdf66d0cb481a5eea62e1f98e71d9520">XAxiPcie_ClearPendingInterrupts</a> (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *InstancePtr, u32 ClearMask)</td></tr>
<tr class="memdesc:gabdf66d0cb481a5eea62e1f98e71d9520"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the currently pending interrupt bits of the IP passed from the caller into "ClearMask".  <a href="#gabdf66d0cb481a5eea62e1f98e71d9520">More...</a><br /></td></tr>
<tr class="separator:gabdf66d0cb481a5eea62e1f98e71d9520"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Registers</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpa9682ea50df45368189078864618a7cd"></a>Register offsets for this device.</p>
<p>Some of the registers are configurable at hardware build time such that may or may not exist in the hardware. </p>
</td></tr>
<tr class="memitem:ga7cecef23e8a28935226e7dc9815390c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga7cecef23e8a28935226e7dc9815390c0">XAXIPCIE_PCIE_CORE_OFFSET</a>&#160;&#160;&#160;0x000</td></tr>
<tr class="memdesc:ga7cecef23e8a28935226e7dc9815390c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCI Express hard core configuration register offset.  <a href="#ga7cecef23e8a28935226e7dc9815390c0">More...</a><br /></td></tr>
<tr class="separator:ga7cecef23e8a28935226e7dc9815390c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf01ed785ab64d6c124437532ece335ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaf01ed785ab64d6c124437532ece335ce">XAXIPCIE_VSECC_OFFSET</a>&#160;&#160;&#160;0x128</td></tr>
<tr class="memdesc:gaf01ed785ab64d6c124437532ece335ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">VSEC Capability Register.  <a href="#gaf01ed785ab64d6c124437532ece335ce">More...</a><br /></td></tr>
<tr class="separator:gaf01ed785ab64d6c124437532ece335ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab99ecd675b55df50a385fc7b429d38e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gab99ecd675b55df50a385fc7b429d38e4">XAXIPCIE_VSECH_OFFSET</a>&#160;&#160;&#160;0x12C</td></tr>
<tr class="memdesc:gab99ecd675b55df50a385fc7b429d38e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">VSEC Header Register.  <a href="#gab99ecd675b55df50a385fc7b429d38e4">More...</a><br /></td></tr>
<tr class="separator:gab99ecd675b55df50a385fc7b429d38e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f8bb352119692caff9e7851fe534498"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga9f8bb352119692caff9e7851fe534498">XAXIPCIE_BI_OFFSET</a>&#160;&#160;&#160;0x130</td></tr>
<tr class="memdesc:ga9f8bb352119692caff9e7851fe534498"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge Info Register.  <a href="#ga9f8bb352119692caff9e7851fe534498">More...</a><br /></td></tr>
<tr class="separator:ga9f8bb352119692caff9e7851fe534498"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10e385edef3931106642fcf07d5a5fec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga10e385edef3931106642fcf07d5a5fec">XAXIPCIE_BSC_OFFSET</a>&#160;&#160;&#160;0x134</td></tr>
<tr class="memdesc:ga10e385edef3931106642fcf07d5a5fec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge Status and Control Register.  <a href="#ga10e385edef3931106642fcf07d5a5fec">More...</a><br /></td></tr>
<tr class="separator:ga10e385edef3931106642fcf07d5a5fec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf4ee25f8cd866c3c4c79bd9f1a784a7c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaf4ee25f8cd866c3c4c79bd9f1a784a7c">XAXIPCIE_ID_OFFSET</a>&#160;&#160;&#160;0x138</td></tr>
<tr class="memdesc:gaf4ee25f8cd866c3c4c79bd9f1a784a7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Decode Register.  <a href="#gaf4ee25f8cd866c3c4c79bd9f1a784a7c">More...</a><br /></td></tr>
<tr class="separator:gaf4ee25f8cd866c3c4c79bd9f1a784a7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad798e4bbf2fc4fe5135dfa56fac31399"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gad798e4bbf2fc4fe5135dfa56fac31399">XAXIPCIE_IM_OFFSET</a>&#160;&#160;&#160;0x13C</td></tr>
<tr class="memdesc:gad798e4bbf2fc4fe5135dfa56fac31399"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Mask Register.  <a href="#gad798e4bbf2fc4fe5135dfa56fac31399">More...</a><br /></td></tr>
<tr class="separator:gad798e4bbf2fc4fe5135dfa56fac31399"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8a758a6bb3b73be59a403a53ef97881"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gae8a758a6bb3b73be59a403a53ef97881">XAXIPCIE_BL_OFFSET</a>&#160;&#160;&#160;0x140</td></tr>
<tr class="memdesc:gae8a758a6bb3b73be59a403a53ef97881"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Location Register.  <a href="#gae8a758a6bb3b73be59a403a53ef97881">More...</a><br /></td></tr>
<tr class="separator:gae8a758a6bb3b73be59a403a53ef97881"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84f89f155288e2a5de41a09bdf5d8672"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga84f89f155288e2a5de41a09bdf5d8672">XAXIPCIE_PHYSC_OFFSET</a>&#160;&#160;&#160;0x144</td></tr>
<tr class="memdesc:ga84f89f155288e2a5de41a09bdf5d8672"><td class="mdescLeft">&#160;</td><td class="mdescRight">Physical status and Control Register.  <a href="#ga84f89f155288e2a5de41a09bdf5d8672">More...</a><br /></td></tr>
<tr class="separator:ga84f89f155288e2a5de41a09bdf5d8672"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb8cd2a16037d697cf4a5af55506af44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gafb8cd2a16037d697cf4a5af55506af44">XAXIPCIE_RPSC_OFFSET</a>&#160;&#160;&#160;0x148</td></tr>
<tr class="memdesc:gafb8cd2a16037d697cf4a5af55506af44"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Status &amp; Control Register.  <a href="#gafb8cd2a16037d697cf4a5af55506af44">More...</a><br /></td></tr>
<tr class="separator:gafb8cd2a16037d697cf4a5af55506af44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b498715d2bbafc1a81fea7abd853f29"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga5b498715d2bbafc1a81fea7abd853f29">XAXIPCIE_RPMSIB_UPPER_OFFSET</a>&#160;&#160;&#160;0x14C</td></tr>
<tr class="memdesc:ga5b498715d2bbafc1a81fea7abd853f29"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port MSI Base 1 Register Upper 32 bits from 64 bit address are written.  <a href="#ga5b498715d2bbafc1a81fea7abd853f29">More...</a><br /></td></tr>
<tr class="separator:ga5b498715d2bbafc1a81fea7abd853f29"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fff8ece26635ba08deb9dd05f6283a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga7fff8ece26635ba08deb9dd05f6283a1">XAXIPCIE_RPMSIB_LOWER_OFFSET</a>&#160;&#160;&#160;0x150</td></tr>
<tr class="memdesc:ga7fff8ece26635ba08deb9dd05f6283a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port MSI Base 2 Register Lower 32 bits from 64 bit address are written.  <a href="#ga7fff8ece26635ba08deb9dd05f6283a1">More...</a><br /></td></tr>
<tr class="separator:ga7fff8ece26635ba08deb9dd05f6283a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e3c116efe4ad6fc7c0d87a4fdea9dab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga8e3c116efe4ad6fc7c0d87a4fdea9dab">XAXIPCIE_RPEFR_OFFSET</a>&#160;&#160;&#160;0x154</td></tr>
<tr class="memdesc:ga8e3c116efe4ad6fc7c0d87a4fdea9dab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Read Register.  <a href="#ga8e3c116efe4ad6fc7c0d87a4fdea9dab">More...</a><br /></td></tr>
<tr class="separator:ga8e3c116efe4ad6fc7c0d87a4fdea9dab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad61ae31bb34ed3e02243c5d74ac75afa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gad61ae31bb34ed3e02243c5d74ac75afa">XAXIPCIE_RPIFR1_OFFSET</a>&#160;&#160;&#160;0x158</td></tr>
<tr class="memdesc:gad61ae31bb34ed3e02243c5d74ac75afa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Read1 Register.  <a href="#gad61ae31bb34ed3e02243c5d74ac75afa">More...</a><br /></td></tr>
<tr class="separator:gad61ae31bb34ed3e02243c5d74ac75afa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga92a83142f665f34045a5235732060c47"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga92a83142f665f34045a5235732060c47">XAXIPCIE_RPIFR2_OFFSET</a>&#160;&#160;&#160;0x15C</td></tr>
<tr class="memdesc:ga92a83142f665f34045a5235732060c47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Read2 Register.  <a href="#ga92a83142f665f34045a5235732060c47">More...</a><br /></td></tr>
<tr class="separator:ga92a83142f665f34045a5235732060c47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace702755df9d438185fdb96c5e63cc0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gace702755df9d438185fdb96c5e63cc0e">XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET</a>&#160;&#160;&#160;0x208</td></tr>
<tr class="memdesc:gace702755df9d438185fdb96c5e63cc0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR 2 PCIBAR translation 0 upper 32 bits.  <a href="#gace702755df9d438185fdb96c5e63cc0e">More...</a><br /></td></tr>
<tr class="separator:gace702755df9d438185fdb96c5e63cc0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa01b566fdaa57bf0696c4a4445053158"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaa01b566fdaa57bf0696c4a4445053158">XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET</a>&#160;&#160;&#160;0x20C</td></tr>
<tr class="memdesc:gaa01b566fdaa57bf0696c4a4445053158"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 0 lower 32 bits.  <a href="#gaa01b566fdaa57bf0696c4a4445053158">More...</a><br /></td></tr>
<tr class="separator:gaa01b566fdaa57bf0696c4a4445053158"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf2f3ccb2ad35296c9ad8fbd7658cfc9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gadf2f3ccb2ad35296c9ad8fbd7658cfc9">XAXIPCIE_AXIBAR2PCIBAR_1U_OFFSET</a>&#160;&#160;&#160;0x210</td></tr>
<tr class="memdesc:gadf2f3ccb2ad35296c9ad8fbd7658cfc9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 1 upper 32 bits.  <a href="#gadf2f3ccb2ad35296c9ad8fbd7658cfc9">More...</a><br /></td></tr>
<tr class="separator:gadf2f3ccb2ad35296c9ad8fbd7658cfc9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6abf854a95cdb33425df188de3e63491"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga6abf854a95cdb33425df188de3e63491">XAXIPCIE_AXIBAR2PCIBAR_1L_OFFSET</a>&#160;&#160;&#160;0x214</td></tr>
<tr class="memdesc:ga6abf854a95cdb33425df188de3e63491"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 1 lower 32 bits.  <a href="#ga6abf854a95cdb33425df188de3e63491">More...</a><br /></td></tr>
<tr class="separator:ga6abf854a95cdb33425df188de3e63491"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac6b872ead955b2775dfd68c8cdaece4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gac6b872ead955b2775dfd68c8cdaece4b">XAXIPCIE_AXIBAR2PCIBAR_2U_OFFSET</a>&#160;&#160;&#160;0x218</td></tr>
<tr class="memdesc:gac6b872ead955b2775dfd68c8cdaece4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 2 upper 32 bits.  <a href="#gac6b872ead955b2775dfd68c8cdaece4b">More...</a><br /></td></tr>
<tr class="separator:gac6b872ead955b2775dfd68c8cdaece4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60190c47d9ac660c226563032207ebb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga60190c47d9ac660c226563032207ebb3">XAXIPCIE_AXIBAR2PCIBAR_2L_OFFSET</a>&#160;&#160;&#160;0x21C</td></tr>
<tr class="memdesc:ga60190c47d9ac660c226563032207ebb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 2 lower 32 bits.  <a href="#ga60190c47d9ac660c226563032207ebb3">More...</a><br /></td></tr>
<tr class="separator:ga60190c47d9ac660c226563032207ebb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3934606610a905f1902a34760c20b7a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga3934606610a905f1902a34760c20b7a8">XAXIPCIE_AXIBAR2PCIBAR_3U_OFFSET</a>&#160;&#160;&#160;0x220</td></tr>
<tr class="memdesc:ga3934606610a905f1902a34760c20b7a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 3 upper 32 bits.  <a href="#ga3934606610a905f1902a34760c20b7a8">More...</a><br /></td></tr>
<tr class="separator:ga3934606610a905f1902a34760c20b7a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga165a875ba9d89b26ebb25cb288c33745"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga165a875ba9d89b26ebb25cb288c33745">XAXIPCIE_AXIBAR2PCIBAR_3L_OFFSET</a>&#160;&#160;&#160;0x224</td></tr>
<tr class="memdesc:ga165a875ba9d89b26ebb25cb288c33745"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 3 lower 32 bits.  <a href="#ga165a875ba9d89b26ebb25cb288c33745">More...</a><br /></td></tr>
<tr class="separator:ga165a875ba9d89b26ebb25cb288c33745"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7970a09db54b7f198a039211a1116b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaa7970a09db54b7f198a039211a1116b3">XAXIPCIE_AXIBAR2PCIBAR_4U_OFFSET</a>&#160;&#160;&#160;0x228</td></tr>
<tr class="memdesc:gaa7970a09db54b7f198a039211a1116b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 4 upper 32 bits.  <a href="#gaa7970a09db54b7f198a039211a1116b3">More...</a><br /></td></tr>
<tr class="separator:gaa7970a09db54b7f198a039211a1116b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga940f71ca9d3e3bc7ac6716f2f34c4884"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga940f71ca9d3e3bc7ac6716f2f34c4884">XAXIPCIE_AXIBAR2PCIBAR_4L_OFFSET</a>&#160;&#160;&#160;0x22C</td></tr>
<tr class="memdesc:ga940f71ca9d3e3bc7ac6716f2f34c4884"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 4 lower 32 bits.  <a href="#ga940f71ca9d3e3bc7ac6716f2f34c4884">More...</a><br /></td></tr>
<tr class="separator:ga940f71ca9d3e3bc7ac6716f2f34c4884"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe4237b20c412dc42cbd47c8bd87af92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gabe4237b20c412dc42cbd47c8bd87af92">XAXIPCIE_AXIBAR2PCIBAR_5U_OFFSET</a>&#160;&#160;&#160;0x230</td></tr>
<tr class="memdesc:gabe4237b20c412dc42cbd47c8bd87af92"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 5 upper 32 bits.  <a href="#gabe4237b20c412dc42cbd47c8bd87af92">More...</a><br /></td></tr>
<tr class="separator:gabe4237b20c412dc42cbd47c8bd87af92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga400d8b2257870a70418b3d9bf8de5a77"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga400d8b2257870a70418b3d9bf8de5a77">XAXIPCIE_AXIBAR2PCIBAR_5L_OFFSET</a>&#160;&#160;&#160;0x234</td></tr>
<tr class="memdesc:ga400d8b2257870a70418b3d9bf8de5a77"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 5 lower 32 bits.  <a href="#ga400d8b2257870a70418b3d9bf8de5a77">More...</a><br /></td></tr>
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VSECC Register bitmaps and masks</h2></td></tr>
<tr class="memitem:gabd84445ebce4bfcb25ca5b75799bbba5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gabd84445ebce4bfcb25ca5b75799bbba5">XAXIPCIE_VSECC_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:gabd84445ebce4bfcb25ca5b75799bbba5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec capability Id.  <a href="#gabd84445ebce4bfcb25ca5b75799bbba5">More...</a><br /></td></tr>
<tr class="separator:gabd84445ebce4bfcb25ca5b75799bbba5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8724baa412ffd4bd593fd67c2928c3a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga8724baa412ffd4bd593fd67c2928c3a1">XAXIPCIE_VSECC_VER_MASK</a>&#160;&#160;&#160;0x000F0000</td></tr>
<tr class="memdesc:ga8724baa412ffd4bd593fd67c2928c3a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version of capability Structure.  <a href="#ga8724baa412ffd4bd593fd67c2928c3a1">More...</a><br /></td></tr>
<tr class="separator:ga8724baa412ffd4bd593fd67c2928c3a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca2f85036ff847a8f3c9def6d402bfe3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaca2f85036ff847a8f3c9def6d402bfe3">XAXIPCIE_VSECC_NEXT_MASK</a>&#160;&#160;&#160;0xFFF00000</td></tr>
<tr class="memdesc:gaca2f85036ff847a8f3c9def6d402bfe3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset to next capability.  <a href="#gaca2f85036ff847a8f3c9def6d402bfe3">More...</a><br /></td></tr>
<tr class="separator:gaca2f85036ff847a8f3c9def6d402bfe3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab791a04d374dfc7d88d5e3c817126b8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gab791a04d374dfc7d88d5e3c817126b8f">XAXIPCIE_VSECC_VER_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gab791a04d374dfc7d88d5e3c817126b8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">VSEC Version shift.  <a href="#gab791a04d374dfc7d88d5e3c817126b8f">More...</a><br /></td></tr>
<tr class="separator:gab791a04d374dfc7d88d5e3c817126b8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4ea49e123b5a60e753034437e748a455"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga4ea49e123b5a60e753034437e748a455">XAXIPCIE_VSECC_NEXT_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:ga4ea49e123b5a60e753034437e748a455"><td class="mdescLeft">&#160;</td><td class="mdescRight">Next capability offset shift.  <a href="#ga4ea49e123b5a60e753034437e748a455">More...</a><br /></td></tr>
<tr class="separator:ga4ea49e123b5a60e753034437e748a455"><td class="memSeparator" colspan="2">&#160;</td></tr>
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VSECH Register bitmaps and masks</h2></td></tr>
<tr class="memitem:gafd846b29aae82d036fc3ea66ef65596f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gafd846b29aae82d036fc3ea66ef65596f">XAXIPCIE_VSECH_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:gafd846b29aae82d036fc3ea66ef65596f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec structure Id.  <a href="#gafd846b29aae82d036fc3ea66ef65596f">More...</a><br /></td></tr>
<tr class="separator:gafd846b29aae82d036fc3ea66ef65596f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94c0af68259b5949d6c003dd85d46b2d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga94c0af68259b5949d6c003dd85d46b2d">XAXIPCIE_VSECH_REV_MASK</a>&#160;&#160;&#160;0x000F0000</td></tr>
<tr class="memdesc:ga94c0af68259b5949d6c003dd85d46b2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec header version.  <a href="#ga94c0af68259b5949d6c003dd85d46b2d">More...</a><br /></td></tr>
<tr class="separator:ga94c0af68259b5949d6c003dd85d46b2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed6b0e6cd2817f7c5c69c3290833447e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaed6b0e6cd2817f7c5c69c3290833447e">XAXIPCIE_VSECH_LEN_MASK</a>&#160;&#160;&#160;0xFFF00000</td></tr>
<tr class="memdesc:gaed6b0e6cd2817f7c5c69c3290833447e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Length of Vsec capability structure.  <a href="#gaed6b0e6cd2817f7c5c69c3290833447e">More...</a><br /></td></tr>
<tr class="separator:gaed6b0e6cd2817f7c5c69c3290833447e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga591f34e1c213bb45aba99629c71b565b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga591f34e1c213bb45aba99629c71b565b">XAXIPCIE_VSECH_REV_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga591f34e1c213bb45aba99629c71b565b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec version shift.  <a href="#ga591f34e1c213bb45aba99629c71b565b">More...</a><br /></td></tr>
<tr class="separator:ga591f34e1c213bb45aba99629c71b565b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa6e2e6e5e712fa8b44077688caee37d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaa6e2e6e5e712fa8b44077688caee37d1">XAXIPCIE_VSECH_LEN_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:gaa6e2e6e5e712fa8b44077688caee37d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec length shift.  <a href="#gaa6e2e6e5e712fa8b44077688caee37d1">More...</a><br /></td></tr>
<tr class="separator:gaa6e2e6e5e712fa8b44077688caee37d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bridge Info Register bitmaps and masks</h2></td></tr>
<tr class="memitem:ga5c3e13956927d814f89b16d58bc87b71"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga5c3e13956927d814f89b16d58bc87b71">XAXIPCIE_BI_GEN2_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga5c3e13956927d814f89b16d58bc87b71"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Gen2 Speed Support Mask.  <a href="#ga5c3e13956927d814f89b16d58bc87b71">More...</a><br /></td></tr>
<tr class="separator:ga5c3e13956927d814f89b16d58bc87b71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab624cf074fe8d343c15a086782e1150c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gab624cf074fe8d343c15a086782e1150c">XAXIPCIE_BI_RP_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gab624cf074fe8d343c15a086782e1150c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Root Port Support.  <a href="#gab624cf074fe8d343c15a086782e1150c">More...</a><br /></td></tr>
<tr class="separator:gab624cf074fe8d343c15a086782e1150c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3950d5b04a69dcbc2e2c5711cb657745"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga3950d5b04a69dcbc2e2c5711cb657745">XAXIPCIE_UP_CONFIG_CAPABLE</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga3950d5b04a69dcbc2e2c5711cb657745"><td class="mdescLeft">&#160;</td><td class="mdescRight">Up Config Capable.  <a href="#ga3950d5b04a69dcbc2e2c5711cb657745">More...</a><br /></td></tr>
<tr class="separator:ga3950d5b04a69dcbc2e2c5711cb657745"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d99e62d5248da57465cd526eaf9cb01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga2d99e62d5248da57465cd526eaf9cb01">XAXIPCIE_BI_ECAM_SIZE_MASK</a>&#160;&#160;&#160;0x00070000</td></tr>
<tr class="memdesc:ga2d99e62d5248da57465cd526eaf9cb01"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECAM size.  <a href="#ga2d99e62d5248da57465cd526eaf9cb01">More...</a><br /></td></tr>
<tr class="separator:ga2d99e62d5248da57465cd526eaf9cb01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae20709cf0062b87ed8689af2e8ee0a0a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gae20709cf0062b87ed8689af2e8ee0a0a">XAXIPCIE_BI_RP_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gae20709cf0062b87ed8689af2e8ee0a0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Root Port Shift.  <a href="#gae20709cf0062b87ed8689af2e8ee0a0a">More...</a><br /></td></tr>
<tr class="separator:gae20709cf0062b87ed8689af2e8ee0a0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e5ee78d2b39fa90a87fea37ed49d35a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga6e5ee78d2b39fa90a87fea37ed49d35a">XAXIPCIE_BI_ECAM_SIZE_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga6e5ee78d2b39fa90a87fea37ed49d35a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe ECAM Size Shift.  <a href="#ga6e5ee78d2b39fa90a87fea37ed49d35a">More...</a><br /></td></tr>
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Bridge Status &amp; Control Register bitmaps and masks</h2></td></tr>
<tr class="memitem:gabfb6e478c3f181fcec8e4918f9442296"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gabfb6e478c3f181fcec8e4918f9442296">XAXIPCIE_BSC_ECAM_BUSY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gabfb6e478c3f181fcec8e4918f9442296"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECAM Busy Status.  <a href="#gabfb6e478c3f181fcec8e4918f9442296">More...</a><br /></td></tr>
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<tr class="memitem:ga6a80436f1d395be5d4963d3f9d09f49c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga6a80436f1d395be5d4963d3f9d09f49c">XAXIPCIE_BSC_GI_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga6a80436f1d395be5d4963d3f9d09f49c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Disable.  <a href="#ga6a80436f1d395be5d4963d3f9d09f49c">More...</a><br /></td></tr>
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<tr class="memitem:ga5d8d34b56c828dc51ee2bf7fe5876e6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga5d8d34b56c828dc51ee2bf7fe5876e6d">XAXIPCIE_BSC_RW1C_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:ga5d8d34b56c828dc51ee2bf7fe5876e6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">RW Permissions to RW1C Registers.  <a href="#ga5d8d34b56c828dc51ee2bf7fe5876e6d">More...</a><br /></td></tr>
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<tr class="memitem:ga7414766d143e8d20bf6ace5ca03548d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga7414766d143e8d20bf6ace5ca03548d8">XAXIPCIE_BSC_RO_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:ga7414766d143e8d20bf6ace5ca03548d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">RW Permissions to RO Registers.  <a href="#ga7414766d143e8d20bf6ace5ca03548d8">More...</a><br /></td></tr>
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<tr class="memitem:ga92e6aa96f3a966ac3ac8b8b00bb770e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga92e6aa96f3a966ac3ac8b8b00bb770e6">XAXIPCIE_BSC_GI_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga92e6aa96f3a966ac3ac8b8b00bb770e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Disable Shift.  <a href="#ga92e6aa96f3a966ac3ac8b8b00bb770e6">More...</a><br /></td></tr>
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<tr class="memitem:gac17ec341d56663eee8c61f478078e8e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gac17ec341d56663eee8c61f478078e8e5">XAXIPCIE_BSC_RW1C_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gac17ec341d56663eee8c61f478078e8e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">RW1C Shift.  <a href="#gac17ec341d56663eee8c61f478078e8e5">More...</a><br /></td></tr>
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<tr class="memitem:ga00ae2b626af9f11c9e3f9ccf4cbbd526"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga00ae2b626af9f11c9e3f9ccf4cbbd526">XAXIPCIE_BSC_RO_SHIFT</a>&#160;&#160;&#160;17</td></tr>
<tr class="memdesc:ga00ae2b626af9f11c9e3f9ccf4cbbd526"><td class="mdescLeft">&#160;</td><td class="mdescRight">RO as RW Shift.  <a href="#ga00ae2b626af9f11c9e3f9ccf4cbbd526">More...</a><br /></td></tr>
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Interrupt Decode Register bitmaps and masks</h2></td></tr>
<tr class="memitem:ga7d8d223d3881fc8e39d0d176974a5f97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga7d8d223d3881fc8e39d0d176974a5f97">XAXIPCIE_ID_LINK_DOWN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga7d8d223d3881fc8e39d0d176974a5f97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Down Mask.  <a href="#ga7d8d223d3881fc8e39d0d176974a5f97">More...</a><br /></td></tr>
<tr class="separator:ga7d8d223d3881fc8e39d0d176974a5f97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac24578f59c89ad7e659b6321259e005c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gac24578f59c89ad7e659b6321259e005c">XAXIPCIE_ID_ECRC_ERR_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gac24578f59c89ad7e659b6321259e005c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Packet CRC failed.  <a href="#gac24578f59c89ad7e659b6321259e005c">More...</a><br /></td></tr>
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<tr class="memitem:gac12ef40af613a60dd229b11010e850ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gac12ef40af613a60dd229b11010e850ef">XAXIPCIE_ID_STR_ERR_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gac12ef40af613a60dd229b11010e850ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Streaming Error Mask.  <a href="#gac12ef40af613a60dd229b11010e850ef">More...</a><br /></td></tr>
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<tr class="memitem:gab7c127293e67e001584800088d052fee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gab7c127293e67e001584800088d052fee">XAXIPCIE_ID_HOT_RST_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gab7c127293e67e001584800088d052fee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Hot Reset Mask.  <a href="#gab7c127293e67e001584800088d052fee">More...</a><br /></td></tr>
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<tr class="memitem:ga846f47d9802bd878b3903c27673e4242"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga846f47d9802bd878b3903c27673e4242">XAXIPCIE_ID_CFG_COMPL_STATE_MASK</a>&#160;&#160;&#160;0x000000E0</td></tr>
<tr class="memdesc:ga846f47d9802bd878b3903c27673e4242"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cfg Completion Status Mask.  <a href="#ga846f47d9802bd878b3903c27673e4242">More...</a><br /></td></tr>
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<tr class="memitem:ga5d2598bc52c54ea03294b1ddd915611a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga5d2598bc52c54ea03294b1ddd915611a">XAXIPCIE_ID_CFG_TIMEOUT_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga5d2598bc52c54ea03294b1ddd915611a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cfg timeout Mask.  <a href="#ga5d2598bc52c54ea03294b1ddd915611a">More...</a><br /></td></tr>
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<tr class="memitem:ga96cd9b31642245e067b4f746cd38a238"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga96cd9b31642245e067b4f746cd38a238">XAXIPCIE_ID_CORRECTABLE_ERR_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga96cd9b31642245e067b4f746cd38a238"><td class="mdescLeft">&#160;</td><td class="mdescRight">Correctable Error Mask.  <a href="#ga96cd9b31642245e067b4f746cd38a238">More...</a><br /></td></tr>
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<tr class="memitem:ga79e63cd543f66440b3b227807636ee90"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga79e63cd543f66440b3b227807636ee90">XAXIPCIE_ID_NONFATAL_ERR_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga79e63cd543f66440b3b227807636ee90"><td class="mdescLeft">&#160;</td><td class="mdescRight">Non-Fatal Error Mask.  <a href="#ga79e63cd543f66440b3b227807636ee90">More...</a><br /></td></tr>
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<tr class="memitem:ga193020c952d0d7ad38a3769887bd9d34"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga193020c952d0d7ad38a3769887bd9d34">XAXIPCIE_ID_FATAL_ERR_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga193020c952d0d7ad38a3769887bd9d34"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fatal Error Mask.  <a href="#ga193020c952d0d7ad38a3769887bd9d34">More...</a><br /></td></tr>
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<tr class="memitem:gacad1e038951dbef989a1d3b266af35c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gacad1e038951dbef989a1d3b266af35c9">XAXIPCIE_ID_INTX_INTERRUPT</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:gacad1e038951dbef989a1d3b266af35c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">INTX Interrupt.  <a href="#gacad1e038951dbef989a1d3b266af35c9">More...</a><br /></td></tr>
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<tr class="memitem:gaf6f510e8eb119a47dd7f0ebc16801fac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaf6f510e8eb119a47dd7f0ebc16801fac">XAXIPCIE_ID_MSI_INTERRUPT</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:gaf6f510e8eb119a47dd7f0ebc16801fac"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI Interrupt.  <a href="#gaf6f510e8eb119a47dd7f0ebc16801fac">More...</a><br /></td></tr>
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<tr class="memitem:gaa428513b46014681de2bf99c3cfac84e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaa428513b46014681de2bf99c3cfac84e">XAXIPCIE_ID_UNSUPP_CMPL_MASK</a>&#160;&#160;&#160;0x00100000</td></tr>
<tr class="memdesc:gaa428513b46014681de2bf99c3cfac84e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Unsupported Request Mask.  <a href="#gaa428513b46014681de2bf99c3cfac84e">More...</a><br /></td></tr>
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<tr class="memitem:ga16dc91d210fc5079a0c4aa475946818f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga16dc91d210fc5079a0c4aa475946818f">XAXIPCIE_ID_UNEXP_CMPL_MASK</a>&#160;&#160;&#160;0x00200000</td></tr>
<tr class="memdesc:ga16dc91d210fc5079a0c4aa475946818f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Unexpected Completion Mask.  <a href="#ga16dc91d210fc5079a0c4aa475946818f">More...</a><br /></td></tr>
<tr class="separator:ga16dc91d210fc5079a0c4aa475946818f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab0f88e6f4f242c99bd926d5db15cdb08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gab0f88e6f4f242c99bd926d5db15cdb08">XAXIPCIE_ID_CMPL_TIMEOUT_MASK</a>&#160;&#160;&#160;0x00400000</td></tr>
<tr class="memdesc:gab0f88e6f4f242c99bd926d5db15cdb08"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave completion Time Mask.  <a href="#gab0f88e6f4f242c99bd926d5db15cdb08">More...</a><br /></td></tr>
<tr class="separator:gab0f88e6f4f242c99bd926d5db15cdb08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1298f6ace7fb8944f15181c960a90beb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga1298f6ace7fb8944f15181c960a90beb">XAXIPCIE_ID_SLV_EP_MASK</a>&#160;&#160;&#160;0x00800000</td></tr>
<tr class="memdesc:ga1298f6ace7fb8944f15181c960a90beb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Error Poison Mask.  <a href="#ga1298f6ace7fb8944f15181c960a90beb">More...</a><br /></td></tr>
<tr class="separator:ga1298f6ace7fb8944f15181c960a90beb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d1319467ba4179502a8b4ef33bf4fe7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga9d1319467ba4179502a8b4ef33bf4fe7">XAXIPCIE_ID_CMPL_ABT_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:ga9d1319467ba4179502a8b4ef33bf4fe7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave completion Abort Mask.  <a href="#ga9d1319467ba4179502a8b4ef33bf4fe7">More...</a><br /></td></tr>
<tr class="separator:ga9d1319467ba4179502a8b4ef33bf4fe7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae119f56dec65465b4438531840a8a759"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gae119f56dec65465b4438531840a8a759">XAXIPCIE_ID_ILL_BURST_MASK</a>&#160;&#160;&#160;0x02000000</td></tr>
<tr class="memdesc:gae119f56dec65465b4438531840a8a759"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Illegal Burst Mask.  <a href="#gae119f56dec65465b4438531840a8a759">More...</a><br /></td></tr>
<tr class="separator:gae119f56dec65465b4438531840a8a759"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c5b6ef607113d639e16d43dd05b9405"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga2c5b6ef607113d639e16d43dd05b9405">XAXIPCIE_ID_DECODE_ERR_MASK</a>&#160;&#160;&#160;0x04000000</td></tr>
<tr class="memdesc:ga2c5b6ef607113d639e16d43dd05b9405"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Decode Error Interrupt Mask.  <a href="#ga2c5b6ef607113d639e16d43dd05b9405">More...</a><br /></td></tr>
<tr class="separator:ga2c5b6ef607113d639e16d43dd05b9405"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa6dd437acd81c0284bfd1ed1563cfbb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaa6dd437acd81c0284bfd1ed1563cfbb7">XAXIPCIE_ID_SLAVE_ERR_MASK</a>&#160;&#160;&#160;0x08000000</td></tr>
<tr class="memdesc:gaa6dd437acd81c0284bfd1ed1563cfbb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Slave Error Interrupt Mask.  <a href="#gaa6dd437acd81c0284bfd1ed1563cfbb7">More...</a><br /></td></tr>
<tr class="separator:gaa6dd437acd81c0284bfd1ed1563cfbb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96036ca77a405418f7e6da47d252f6c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga96036ca77a405418f7e6da47d252f6c9">XAXIPCIE_ID_MASTER_EP_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:ga96036ca77a405418f7e6da47d252f6c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Error Poison Mask.  <a href="#ga96036ca77a405418f7e6da47d252f6c9">More...</a><br /></td></tr>
<tr class="separator:ga96036ca77a405418f7e6da47d252f6c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb7c330e5d10623ceafc66dd08f149ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaeb7c330e5d10623ceafc66dd08f149ea">XAXIPCIE_ID_CLEAR_ALL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:gaeb7c330e5d10623ceafc66dd08f149ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask of all Interrupts.  <a href="#gaeb7c330e5d10623ceafc66dd08f149ea">More...</a><br /></td></tr>
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Interrupt Mask Register bitmaps and masks</h2></td></tr>
<tr class="memitem:ga40d5e3c669642af8441aed4d5ad23ee2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga40d5e3c669642af8441aed4d5ad23ee2">XAXIPCIE_IM_ENABLE_ALL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga40d5e3c669642af8441aed4d5ad23ee2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable All Interrupts.  <a href="#ga40d5e3c669642af8441aed4d5ad23ee2">More...</a><br /></td></tr>
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<tr class="memitem:ga1da6c8b6280b6726d8ac6178bf11af15"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga1da6c8b6280b6726d8ac6178bf11af15">XAXIPCIE_IM_DISABLE_ALL_MASK</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:ga1da6c8b6280b6726d8ac6178bf11af15"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable All Interrupts.  <a href="#ga1da6c8b6280b6726d8ac6178bf11af15">More...</a><br /></td></tr>
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Bus Location Register bitmaps and masks</h2></td></tr>
<tr class="memitem:ga269fecd1e2d8010e7b84e1339a5b2b94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga269fecd1e2d8010e7b84e1339a5b2b94">XAXIPCIE_BL_FUNC_MASK</a>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="memdesc:ga269fecd1e2d8010e7b84e1339a5b2b94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Function Number.  <a href="#ga269fecd1e2d8010e7b84e1339a5b2b94">More...</a><br /></td></tr>
<tr class="separator:ga269fecd1e2d8010e7b84e1339a5b2b94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21a35da125896346b1a3219fe2dfcc93"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga21a35da125896346b1a3219fe2dfcc93">XAXIPCIE_BL_DEV_MASK</a>&#160;&#160;&#160;0x000000F8</td></tr>
<tr class="memdesc:ga21a35da125896346b1a3219fe2dfcc93"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Device Number.  <a href="#ga21a35da125896346b1a3219fe2dfcc93">More...</a><br /></td></tr>
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<tr class="memitem:gaf8a11f087363d5ff57409bf45a597851"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaf8a11f087363d5ff57409bf45a597851">XAXIPCIE_BL_BUS_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:gaf8a11f087363d5ff57409bf45a597851"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Bus Number.  <a href="#gaf8a11f087363d5ff57409bf45a597851">More...</a><br /></td></tr>
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<tr class="memitem:gae40bca0b490429edd0c59df2f04dd595"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gae40bca0b490429edd0c59df2f04dd595">XAXIPCIE_BL_PORT_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gae40bca0b490429edd0c59df2f04dd595"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Port Number.  <a href="#gae40bca0b490429edd0c59df2f04dd595">More...</a><br /></td></tr>
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<tr class="memitem:gaf0d3ce908be6f6c89a7212ddc42ba192"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaf0d3ce908be6f6c89a7212ddc42ba192">XAXIPCIE_BL_DEV_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gaf0d3ce908be6f6c89a7212ddc42ba192"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Device Number Shift Value.  <a href="#gaf0d3ce908be6f6c89a7212ddc42ba192">More...</a><br /></td></tr>
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<tr class="memitem:gadc5afc68e0ece36131a9636a467ab327"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gadc5afc68e0ece36131a9636a467ab327">XAXIPCIE_BL_BUS_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gadc5afc68e0ece36131a9636a467ab327"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Bus Number Shift Value.  <a href="#gadc5afc68e0ece36131a9636a467ab327">More...</a><br /></td></tr>
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<tr class="memitem:ga7ef6bab98d1eba6156f808f92e39d7f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga7ef6bab98d1eba6156f808f92e39d7f2">XAXIPCIE_BL_PORT_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga7ef6bab98d1eba6156f808f92e39d7f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Bus Number Shift Value.  <a href="#ga7ef6bab98d1eba6156f808f92e39d7f2">More...</a><br /></td></tr>
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PHY Status &amp; Control Register bitmaps and masks</h2></td></tr>
<tr class="memitem:ga1238d2aba155c18a5ce7b45d2a1cbe39"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga1238d2aba155c18a5ce7b45d2a1cbe39">XAXIPCIE_PHYSC_LINK_RATE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga1238d2aba155c18a5ce7b45d2a1cbe39"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Rate.  <a href="#ga1238d2aba155c18a5ce7b45d2a1cbe39">More...</a><br /></td></tr>
<tr class="separator:ga1238d2aba155c18a5ce7b45d2a1cbe39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1afe809e17692a8fac45d860ac99c4d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga1afe809e17692a8fac45d860ac99c4d3">XAXIPCIE_PHYSC_LINK_WIDTH_MASK</a>&#160;&#160;&#160;0x00000006</td></tr>
<tr class="memdesc:ga1afe809e17692a8fac45d860ac99c4d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Width Mask.  <a href="#ga1afe809e17692a8fac45d860ac99c4d3">More...</a><br /></td></tr>
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<tr class="memitem:ga83dbe369846939579a0dd3d74476bcb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga83dbe369846939579a0dd3d74476bcb7">XAXIPCIE_PHYSC_LTSSM_STATE_MASK</a>&#160;&#160;&#160;0x000001F8</td></tr>
<tr class="memdesc:ga83dbe369846939579a0dd3d74476bcb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">LTSSM State Mask.  <a href="#ga83dbe369846939579a0dd3d74476bcb7">More...</a><br /></td></tr>
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<tr class="memitem:ga1d873d3497027ad74b8d0240a28ab11d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga1d873d3497027ad74b8d0240a28ab11d">XAXIPCIE_PHYSC_LANE_REV_MASK</a>&#160;&#160;&#160;0x00000600</td></tr>
<tr class="memdesc:ga1d873d3497027ad74b8d0240a28ab11d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane Reversal Mask.  <a href="#ga1d873d3497027ad74b8d0240a28ab11d">More...</a><br /></td></tr>
<tr class="separator:ga1d873d3497027ad74b8d0240a28ab11d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b1c63c3222b1c3585b7b7ba73a46db8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga1b1c63c3222b1c3585b7b7ba73a46db8">XAXIPCIE_PHYSC_LINK_UP_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga1b1c63c3222b1c3585b7b7ba73a46db8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Up Status Mask.  <a href="#ga1b1c63c3222b1c3585b7b7ba73a46db8">More...</a><br /></td></tr>
<tr class="separator:ga1b1c63c3222b1c3585b7b7ba73a46db8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga238bcf6752996345861f9e958ee5bddc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga238bcf6752996345861f9e958ee5bddc">XAXIPCIE_PHYSC_DLW_MASK</a>&#160;&#160;&#160;0x00030000</td></tr>
<tr class="memdesc:ga238bcf6752996345861f9e958ee5bddc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width to change Mask.  <a href="#ga238bcf6752996345861f9e958ee5bddc">More...</a><br /></td></tr>
<tr class="separator:ga238bcf6752996345861f9e958ee5bddc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga04fd250e831f12d2274e81fc11f8544a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga04fd250e831f12d2274e81fc11f8544a">XAXIPCIE_PHYSC_DLWS_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:ga04fd250e831f12d2274e81fc11f8544a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width Speed to change Mask.  <a href="#ga04fd250e831f12d2274e81fc11f8544a">More...</a><br /></td></tr>
<tr class="separator:ga04fd250e831f12d2274e81fc11f8544a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf6ed374b48c1d8d127a3cc0fa1dd082"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaaf6ed374b48c1d8d127a3cc0fa1dd082">XAXIPCIE_PHYSC_DLA_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:gaaf6ed374b48c1d8d127a3cc0fa1dd082"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Change change to reliability or Autonomus Mask.  <a href="#gaaf6ed374b48c1d8d127a3cc0fa1dd082">More...</a><br /></td></tr>
<tr class="separator:gaaf6ed374b48c1d8d127a3cc0fa1dd082"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3422457e569985908990b125ded1b5f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaf3422457e569985908990b125ded1b5f">XAXIPCIE_PHYSC_DLC_MASK</a>&#160;&#160;&#160;0x00300000</td></tr>
<tr class="memdesc:gaf3422457e569985908990b125ded1b5f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link change Mask.  <a href="#gaf3422457e569985908990b125ded1b5f">More...</a><br /></td></tr>
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<tr class="memitem:gaef8ab25bd7ab6a989ddc832c2c50c2e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaef8ab25bd7ab6a989ddc832c2c50c2e4">XAXIPCIE_PHYSC_LINK_WIDTH_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gaef8ab25bd7ab6a989ddc832c2c50c2e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Status Shift.  <a href="#gaef8ab25bd7ab6a989ddc832c2c50c2e4">More...</a><br /></td></tr>
<tr class="separator:gaef8ab25bd7ab6a989ddc832c2c50c2e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga41728830bc4094a6044ea629c4699201"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga41728830bc4094a6044ea629c4699201">XAXIPCIE_PHYSC_LTSSM_STATE_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:ga41728830bc4094a6044ea629c4699201"><td class="mdescLeft">&#160;</td><td class="mdescRight">LTSSM State Shift.  <a href="#ga41728830bc4094a6044ea629c4699201">More...</a><br /></td></tr>
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<tr class="memitem:gad478317d1ca0eae5e32d87e51bbb0a92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gad478317d1ca0eae5e32d87e51bbb0a92">XAXIPCIE_PHYSC_LANE_REV_SHIFT</a>&#160;&#160;&#160;9</td></tr>
<tr class="memdesc:gad478317d1ca0eae5e32d87e51bbb0a92"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane Reversal Shift.  <a href="#gad478317d1ca0eae5e32d87e51bbb0a92">More...</a><br /></td></tr>
<tr class="separator:gad478317d1ca0eae5e32d87e51bbb0a92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6b51f3442219824eb75fc8ff3cfe1660"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga6b51f3442219824eb75fc8ff3cfe1660">XAXIPCIE_PHYSC_LINK_UP_SHIFT</a>&#160;&#160;&#160;11</td></tr>
<tr class="memdesc:ga6b51f3442219824eb75fc8ff3cfe1660"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Up Status Shift.  <a href="#ga6b51f3442219824eb75fc8ff3cfe1660">More...</a><br /></td></tr>
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<tr class="memitem:ga7e9344be85c4daabbe33825ec565e348"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga7e9344be85c4daabbe33825ec565e348">XAXIPCIE_PHYSC_DLW_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga7e9344be85c4daabbe33825ec565e348"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width to change Shift.  <a href="#ga7e9344be85c4daabbe33825ec565e348">More...</a><br /></td></tr>
<tr class="separator:ga7e9344be85c4daabbe33825ec565e348"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab4aba0340f18918d3aa073dfe631724c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gab4aba0340f18918d3aa073dfe631724c">XAXIPCIE_PHYSC_DLWS_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:gab4aba0340f18918d3aa073dfe631724c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width Speed to change Shift.  <a href="#gab4aba0340f18918d3aa073dfe631724c">More...</a><br /></td></tr>
<tr class="separator:gab4aba0340f18918d3aa073dfe631724c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39556f83d4e88ec7783db2826ce5303d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga39556f83d4e88ec7783db2826ce5303d">XAXIPCIE_PHYSC_DLA_SHIFT</a>&#160;&#160;&#160;19</td></tr>
<tr class="memdesc:ga39556f83d4e88ec7783db2826ce5303d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link change to reliability or Autonomus Shift.  <a href="#ga39556f83d4e88ec7783db2826ce5303d">More...</a><br /></td></tr>
<tr class="separator:ga39556f83d4e88ec7783db2826ce5303d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaabf018637b6aa1ca5b7ca4657ed2583a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaabf018637b6aa1ca5b7ca4657ed2583a">XAXIPCIE_PHYSC_DLC_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:gaabf018637b6aa1ca5b7ca4657ed2583a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link change Shift.  <a href="#gaabf018637b6aa1ca5b7ca4657ed2583a">More...</a><br /></td></tr>
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Root Port Status/Control Register bitmaps and masks</h2></td></tr>
<tr class="memitem:ga727eba08077bad1923e3ff44e5522110"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga727eba08077bad1923e3ff44e5522110">XAXIPCIE_RPSC_MASK</a>&#160;&#160;&#160;0x0FFF0001</td></tr>
<tr class="memdesc:ga727eba08077bad1923e3ff44e5522110"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Register mask.  <a href="#ga727eba08077bad1923e3ff44e5522110">More...</a><br /></td></tr>
<tr class="separator:ga727eba08077bad1923e3ff44e5522110"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7239a578a5e3bbf80fac05bab9a841aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga7239a578a5e3bbf80fac05bab9a841aa">XAXIPCIE_RPSC_BRIDGE_ENABLE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga7239a578a5e3bbf80fac05bab9a841aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge Enable Mask.  <a href="#ga7239a578a5e3bbf80fac05bab9a841aa">More...</a><br /></td></tr>
<tr class="separator:ga7239a578a5e3bbf80fac05bab9a841aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga306dded24643ad2589e7773a278198c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga306dded24643ad2589e7773a278198c2">XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:ga306dded24643ad2589e7773a278198c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Not Empty.  <a href="#ga306dded24643ad2589e7773a278198c2">More...</a><br /></td></tr>
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<tr class="memitem:gaad476109c1b88e734cd0c487551ecd38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaad476109c1b88e734cd0c487551ecd38">XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:gaad476109c1b88e734cd0c487551ecd38"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Overflow.  <a href="#gaad476109c1b88e734cd0c487551ecd38">More...</a><br /></td></tr>
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<tr class="memitem:gad174b729ea9da546195a3e35b5306296"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gad174b729ea9da546195a3e35b5306296">XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:gad174b729ea9da546195a3e35b5306296"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Not Empty.  <a href="#gad174b729ea9da546195a3e35b5306296">More...</a><br /></td></tr>
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<tr class="memitem:gae7e2cf8f647b545ca89191d281d28500"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gae7e2cf8f647b545ca89191d281d28500">XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:gae7e2cf8f647b545ca89191d281d28500"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Overflow.  <a href="#gae7e2cf8f647b545ca89191d281d28500">More...</a><br /></td></tr>
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<tr class="memitem:gaae47e36bef3304c2ed171d5c4263b356"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaae47e36bef3304c2ed171d5c4263b356">XAXIPCIE_RPSC_COMP_TIMEOUT_MASK</a>&#160;&#160;&#160;0x0FF00000</td></tr>
<tr class="memdesc:gaae47e36bef3304c2ed171d5c4263b356"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Completion Timeout.  <a href="#gaae47e36bef3304c2ed171d5c4263b356">More...</a><br /></td></tr>
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<tr class="memitem:gae31c1b6a918ba904627c85e1b1e90cd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gae31c1b6a918ba904627c85e1b1e90cd7">XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gae31c1b6a918ba904627c85e1b1e90cd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Empty Shift.  <a href="#gae31c1b6a918ba904627c85e1b1e90cd7">More...</a><br /></td></tr>
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<tr class="memitem:ga4c13191564e035b1f82bd03a2618ae68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga4c13191564e035b1f82bd03a2618ae68">XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_SHIFT</a>&#160;&#160;&#160;17</td></tr>
<tr class="memdesc:ga4c13191564e035b1f82bd03a2618ae68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Overflow Shift.  <a href="#ga4c13191564e035b1f82bd03a2618ae68">More...</a><br /></td></tr>
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<tr class="memitem:gac928e2b08d55a229e1bcb3064c420152"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gac928e2b08d55a229e1bcb3064c420152">XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:gac928e2b08d55a229e1bcb3064c420152"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Empty Shift.  <a href="#gac928e2b08d55a229e1bcb3064c420152">More...</a><br /></td></tr>
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<tr class="memitem:ga487c2d600b1745aeda32d7987c08ba79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga487c2d600b1745aeda32d7987c08ba79">XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_SHIFT</a>&#160;&#160;&#160;19</td></tr>
<tr class="memdesc:ga487c2d600b1745aeda32d7987c08ba79"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Overflow Shift.  <a href="#ga487c2d600b1745aeda32d7987c08ba79">More...</a><br /></td></tr>
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<tr class="memitem:ga5bd566eee0347d55e43ce6c803fd9ea6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga5bd566eee0347d55e43ce6c803fd9ea6">XAXIPCIE_RPSC_COMP_TIMEOUT_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:ga5bd566eee0347d55e43ce6c803fd9ea6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Completion Timeout Shift.  <a href="#ga5bd566eee0347d55e43ce6c803fd9ea6">More...</a><br /></td></tr>
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Root Port MSI Base Register bitmaps and masks</h2></td></tr>
<tr class="memitem:ga6b8ab2e2dd878a06c3fec3bef2612f88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga6b8ab2e2dd878a06c3fec3bef2612f88">XAXIPCIE_RPMSIB_UPPER_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga6b8ab2e2dd878a06c3fec3bef2612f88"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper 32 bits of 64 bit MSI Base Address.  <a href="#ga6b8ab2e2dd878a06c3fec3bef2612f88">More...</a><br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIPCIE_RPMSIB_UPPER_SHIFT</b>&#160;&#160;&#160;32	   /* Shift of Upper 32 bits */</td></tr>
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<tr class="memitem:gac25094bce1e85b534dc154222a7d83a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gac25094bce1e85b534dc154222a7d83a3">XAXIPCIE_RPMSIB_LOWER_MASK</a>&#160;&#160;&#160;0xFFFFF000</td></tr>
<tr class="memdesc:gac25094bce1e85b534dc154222a7d83a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lower 32 bits of 64 bit MSI Base Address.  <a href="#gac25094bce1e85b534dc154222a7d83a3">More...</a><br /></td></tr>
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Root Port Error FIFO Read Register bitmaps and masks</h2></td></tr>
<tr class="memitem:ga4e82350a3eb45f3f8a61351de81d39c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga4e82350a3eb45f3f8a61351de81d39c9">XAXIPCIE_RPEFR_REQ_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga4e82350a3eb45f3f8a61351de81d39c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester of Error Msg.  <a href="#ga4e82350a3eb45f3f8a61351de81d39c9">More...</a><br /></td></tr>
<tr class="separator:ga4e82350a3eb45f3f8a61351de81d39c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga76dd5672aa49d1675193c515ee99275e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga76dd5672aa49d1675193c515ee99275e">XAXIPCIE_RPEFR_ERR_TYPE_MASK</a>&#160;&#160;&#160;0x00030000</td></tr>
<tr class="memdesc:ga76dd5672aa49d1675193c515ee99275e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of Error.  <a href="#ga76dd5672aa49d1675193c515ee99275e">More...</a><br /></td></tr>
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<tr class="memitem:ga0d7406f32c476e78d25f92fab2bbb30b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga0d7406f32c476e78d25f92fab2bbb30b">XAXIPCIE_RPEFR_ERR_VALID_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:ga0d7406f32c476e78d25f92fab2bbb30b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Read Succeeded Status.  <a href="#ga0d7406f32c476e78d25f92fab2bbb30b">More...</a><br /></td></tr>
<tr class="separator:ga0d7406f32c476e78d25f92fab2bbb30b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga285c4d376d023b3b9df54754606808df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga285c4d376d023b3b9df54754606808df">XAXIPCIE_RPEFR_ERR_TYPE_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga285c4d376d023b3b9df54754606808df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of Error Shift.  <a href="#ga285c4d376d023b3b9df54754606808df">More...</a><br /></td></tr>
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<tr class="memitem:gacb9ed69607f6da66cc0501f4f18bb732"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gacb9ed69607f6da66cc0501f4f18bb732">XAXIPCIE_RPEFR_ERR_VALID_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:gacb9ed69607f6da66cc0501f4f18bb732"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Read Succeeded Status Shift.  <a href="#gacb9ed69607f6da66cc0501f4f18bb732">More...</a><br /></td></tr>
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Root Port Interrupt FIFO Read 1 Register bitmaps and masks</h2></td></tr>
<tr class="memitem:ga477d9111e2c1e6932b00b658cda9df01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga477d9111e2c1e6932b00b658cda9df01">XAXIPCIE_RPIFR1_REQ_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga477d9111e2c1e6932b00b658cda9df01"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester Id of Interrupt Message.  <a href="#ga477d9111e2c1e6932b00b658cda9df01">More...</a><br /></td></tr>
<tr class="separator:ga477d9111e2c1e6932b00b658cda9df01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2a9c673eaa9cdb18e3ac3788fcb834d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gad2a9c673eaa9cdb18e3ac3788fcb834d">XAXIPCIE_RPIFR1_MSI_ADDR_MASK</a>&#160;&#160;&#160;0x07FF0000</td></tr>
<tr class="memdesc:gad2a9c673eaa9cdb18e3ac3788fcb834d"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI Address.  <a href="#gad2a9c673eaa9cdb18e3ac3788fcb834d">More...</a><br /></td></tr>
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<tr class="memitem:gaaf545ca193095942641304d55ce7e416"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaaf545ca193095942641304d55ce7e416">XAXIPCIE_RPIFR1_INTR_LINE_MASK</a>&#160;&#160;&#160;0x18000000</td></tr>
<tr class="memdesc:gaaf545ca193095942641304d55ce7e416"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr Line Mask.  <a href="#gaaf545ca193095942641304d55ce7e416">More...</a><br /></td></tr>
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<tr class="memitem:gaa573753049273f1ece6a4b24917d2b05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaa573753049273f1ece6a4b24917d2b05">XAXIPCIE_RPIFR1_INTR_ASSERT_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:gaa573753049273f1ece6a4b24917d2b05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether Interrupt INTx is asserted.  <a href="#gaa573753049273f1ece6a4b24917d2b05">More...</a><br /></td></tr>
<tr class="separator:gaa573753049273f1ece6a4b24917d2b05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d9b70e72dbf4e3db706b28f5f749e74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga9d9b70e72dbf4e3db706b28f5f749e74">XAXIPCIE_RPIFR1_MSIINTR_VALID_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:ga9d9b70e72dbf4e3db706b28f5f749e74"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether Interrupt is MSI or INTx.  <a href="#ga9d9b70e72dbf4e3db706b28f5f749e74">More...</a><br /></td></tr>
<tr class="separator:ga9d9b70e72dbf4e3db706b28f5f749e74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9a5f8ec646e50bdc31887a508f50fc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaf9a5f8ec646e50bdc31887a508f50fc5">XAXIPCIE_RPIFR1_INTR_VALID_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gaf9a5f8ec646e50bdc31887a508f50fc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Read Succeeded Status.  <a href="#gaf9a5f8ec646e50bdc31887a508f50fc5">More...</a><br /></td></tr>
<tr class="separator:gaf9a5f8ec646e50bdc31887a508f50fc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71868428e591d5f59fd40151da6d3aa5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga71868428e591d5f59fd40151da6d3aa5">XAXIPCIE_RPIFR1_MSI_ADDR_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga71868428e591d5f59fd40151da6d3aa5"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI Address Shift.  <a href="#ga71868428e591d5f59fd40151da6d3aa5">More...</a><br /></td></tr>
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<tr class="memitem:ga0465365bbae94b36de39aceeb580cdd1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga0465365bbae94b36de39aceeb580cdd1">XAXIPCIE_RPIFR1_MSIINTR_VALID_SHIFT</a>&#160;&#160;&#160;30</td></tr>
<tr class="memdesc:ga0465365bbae94b36de39aceeb580cdd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI/INTx Interrupt Shift.  <a href="#ga0465365bbae94b36de39aceeb580cdd1">More...</a><br /></td></tr>
<tr class="separator:ga0465365bbae94b36de39aceeb580cdd1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabdd55507fa3a696908e3d31abe7ff1e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gabdd55507fa3a696908e3d31abe7ff1e6">XAXIPCIE_RPIFR1_INTR_VALID_SHIFT</a>&#160;&#160;&#160;31</td></tr>
<tr class="memdesc:gabdd55507fa3a696908e3d31abe7ff1e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Read Valid Shift.  <a href="#gabdd55507fa3a696908e3d31abe7ff1e6">More...</a><br /></td></tr>
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Root Port Interrupt FIFO Read 2 Register bitmaps and masks</h2></td></tr>
<tr class="memitem:gaaf6ce74eb3d24d535f2c399330c27af9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gaaf6ce74eb3d24d535f2c399330c27af9">XAXIPCIE_RPIFR2_MSG_DATA_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:gaaf6ce74eb3d24d535f2c399330c27af9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pay Load for MSI Message.  <a href="#gaaf6ce74eb3d24d535f2c399330c27af9">More...</a><br /></td></tr>
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ECAM Address Register bitmaps and masks</h2></td></tr>
<tr class="memitem:gabbe43193c1a1f1b12a1e8e2910ffb02e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gabbe43193c1a1f1b12a1e8e2910ffb02e">XAXIPCIE_ECAM_MASK</a>&#160;&#160;&#160;0x0FFFFFFF</td></tr>
<tr class="memdesc:gabbe43193c1a1f1b12a1e8e2910ffb02e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask of all valid bits.  <a href="#gabbe43193c1a1f1b12a1e8e2910ffb02e">More...</a><br /></td></tr>
<tr class="separator:gabbe43193c1a1f1b12a1e8e2910ffb02e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39ab6deaee9fe1e2ab734e85dc0fad5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga39ab6deaee9fe1e2ab734e85dc0fad5c">XAXIPCIE_ECAM_BUS_MASK</a>&#160;&#160;&#160;0x0FF00000</td></tr>
<tr class="memdesc:ga39ab6deaee9fe1e2ab734e85dc0fad5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Number Mask.  <a href="#ga39ab6deaee9fe1e2ab734e85dc0fad5c">More...</a><br /></td></tr>
<tr class="separator:ga39ab6deaee9fe1e2ab734e85dc0fad5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c530b27ed7392d44e98855cbf1582fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga7c530b27ed7392d44e98855cbf1582fe">XAXIPCIE_ECAM_DEV_MASK</a>&#160;&#160;&#160;0x000F8000</td></tr>
<tr class="memdesc:ga7c530b27ed7392d44e98855cbf1582fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Number Mask.  <a href="#ga7c530b27ed7392d44e98855cbf1582fe">More...</a><br /></td></tr>
<tr class="separator:ga7c530b27ed7392d44e98855cbf1582fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b3e595d86874d13a20a84e998792ede"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga8b3e595d86874d13a20a84e998792ede">XAXIPCIE_ECAM_FUN_MASK</a>&#160;&#160;&#160;0x00007000</td></tr>
<tr class="memdesc:ga8b3e595d86874d13a20a84e998792ede"><td class="mdescLeft">&#160;</td><td class="mdescRight">Function Number Mask.  <a href="#ga8b3e595d86874d13a20a84e998792ede">More...</a><br /></td></tr>
<tr class="separator:ga8b3e595d86874d13a20a84e998792ede"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad62957cb703c4fdabd125b714ff3b113"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gad62957cb703c4fdabd125b714ff3b113">XAXIPCIE_ECAM_REG_MASK</a>&#160;&#160;&#160;0x00000FFC</td></tr>
<tr class="memdesc:gad62957cb703c4fdabd125b714ff3b113"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register Number Mask.  <a href="#gad62957cb703c4fdabd125b714ff3b113">More...</a><br /></td></tr>
<tr class="separator:gad62957cb703c4fdabd125b714ff3b113"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga188489525792d10a8892af78991ba828"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga188489525792d10a8892af78991ba828">XAXIPCIE_ECAM_BYT_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:ga188489525792d10a8892af78991ba828"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte Address Mask.  <a href="#ga188489525792d10a8892af78991ba828">More...</a><br /></td></tr>
<tr class="separator:ga188489525792d10a8892af78991ba828"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe54d275930774f3ef2fa61861cc1047"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gafe54d275930774f3ef2fa61861cc1047">XAXIPCIE_ECAM_BUS_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:gafe54d275930774f3ef2fa61861cc1047"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Number Shift Value.  <a href="#gafe54d275930774f3ef2fa61861cc1047">More...</a><br /></td></tr>
<tr class="separator:gafe54d275930774f3ef2fa61861cc1047"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8e00362272438c225cdf2bf5ee977e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gad8e00362272438c225cdf2bf5ee977e7">XAXIPCIE_ECAM_DEV_SHIFT</a>&#160;&#160;&#160;15</td></tr>
<tr class="memdesc:gad8e00362272438c225cdf2bf5ee977e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Number Shift Value.  <a href="#gad8e00362272438c225cdf2bf5ee977e7">More...</a><br /></td></tr>
<tr class="separator:gad8e00362272438c225cdf2bf5ee977e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6b61db832dff675f08c9f85b8d51027"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#gad6b61db832dff675f08c9f85b8d51027">XAXIPCIE_ECAM_FUN_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:gad6b61db832dff675f08c9f85b8d51027"><td class="mdescLeft">&#160;</td><td class="mdescRight">Function Number Shift Value.  <a href="#gad6b61db832dff675f08c9f85b8d51027">More...</a><br /></td></tr>
<tr class="separator:gad6b61db832dff675f08c9f85b8d51027"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40dade6a41bec5215be2714e28babe3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga40dade6a41bec5215be2714e28babe3b">XAXIPCIE_ECAM_REG_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga40dade6a41bec5215be2714e28babe3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register Number Shift Value.  <a href="#ga40dade6a41bec5215be2714e28babe3b">More...</a><br /></td></tr>
<tr class="separator:ga40dade6a41bec5215be2714e28babe3b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9b1361bda2147f4bad36f800a61fa056"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie__v3__0.html#ga9b1361bda2147f4bad36f800a61fa056">XAXIPCIE_ECAM_BYT_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga9b1361bda2147f4bad36f800a61fa056"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte Offset Shift Value.  <a href="#ga9b1361bda2147f4bad36f800a61fa056">More...</a><br /></td></tr>
<tr class="separator:ga9b1361bda2147f4bad36f800a61fa056"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="gaa01b566fdaa57bf0696c4a4445053158"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa01b566fdaa57bf0696c4a4445053158">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET&#160;&#160;&#160;0x20C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 0 lower 32 bits. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga19d8a1973231160bdd518b1c62bda3d4">XAxiPcie_GetLocalBusBar2PcieBar()</a>, and <a class="el" href="group__axipcie__v3__0.html#ga51ee29d03fbefc82b9208f46a12d5a06">XAxiPcie_SetLocalBusBar2PcieBar()</a>.</p>

</div>
</div>
<a id="gace702755df9d438185fdb96c5e63cc0e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gace702755df9d438185fdb96c5e63cc0e">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET&#160;&#160;&#160;0x208</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR 2 PCIBAR translation 0 upper 32 bits. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga19d8a1973231160bdd518b1c62bda3d4">XAxiPcie_GetLocalBusBar2PcieBar()</a>, and <a class="el" href="group__axipcie__v3__0.html#ga51ee29d03fbefc82b9208f46a12d5a06">XAxiPcie_SetLocalBusBar2PcieBar()</a>.</p>

</div>
</div>
<a id="ga6abf854a95cdb33425df188de3e63491"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6abf854a95cdb33425df188de3e63491">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_1L_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_1L_OFFSET&#160;&#160;&#160;0x214</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 1 lower 32 bits. </p>

</div>
</div>
<a id="gadf2f3ccb2ad35296c9ad8fbd7658cfc9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadf2f3ccb2ad35296c9ad8fbd7658cfc9">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_1U_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_1U_OFFSET&#160;&#160;&#160;0x210</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 1 upper 32 bits. </p>

</div>
</div>
<a id="ga60190c47d9ac660c226563032207ebb3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga60190c47d9ac660c226563032207ebb3">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_2L_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_2L_OFFSET&#160;&#160;&#160;0x21C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 2 lower 32 bits. </p>

</div>
</div>
<a id="gac6b872ead955b2775dfd68c8cdaece4b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac6b872ead955b2775dfd68c8cdaece4b">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_2U_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_2U_OFFSET&#160;&#160;&#160;0x218</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 2 upper 32 bits. </p>

</div>
</div>
<a id="ga165a875ba9d89b26ebb25cb288c33745"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga165a875ba9d89b26ebb25cb288c33745">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_3L_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_3L_OFFSET&#160;&#160;&#160;0x224</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 3 lower 32 bits. </p>

</div>
</div>
<a id="ga3934606610a905f1902a34760c20b7a8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3934606610a905f1902a34760c20b7a8">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_3U_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_3U_OFFSET&#160;&#160;&#160;0x220</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 3 upper 32 bits. </p>

</div>
</div>
<a id="ga940f71ca9d3e3bc7ac6716f2f34c4884"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga940f71ca9d3e3bc7ac6716f2f34c4884">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_4L_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_4L_OFFSET&#160;&#160;&#160;0x22C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 4 lower 32 bits. </p>

</div>
</div>
<a id="gaa7970a09db54b7f198a039211a1116b3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa7970a09db54b7f198a039211a1116b3">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_4U_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_4U_OFFSET&#160;&#160;&#160;0x228</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 4 upper 32 bits. </p>

</div>
</div>
<a id="ga400d8b2257870a70418b3d9bf8de5a77"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga400d8b2257870a70418b3d9bf8de5a77">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_5L_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_5L_OFFSET&#160;&#160;&#160;0x234</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 5 lower 32 bits. </p>

</div>
</div>
<a id="gabe4237b20c412dc42cbd47c8bd87af92"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabe4237b20c412dc42cbd47c8bd87af92">&#9670;&nbsp;</a></span>XAXIPCIE_AXIBAR2PCIBAR_5U_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_AXIBAR2PCIBAR_5U_OFFSET&#160;&#160;&#160;0x230</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>AXIBAR to PCIBAR translation 5 upper 32 bits. </p>

</div>
</div>
<a id="ga2d99e62d5248da57465cd526eaf9cb01"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga2d99e62d5248da57465cd526eaf9cb01">&#9670;&nbsp;</a></span>XAXIPCIE_BI_ECAM_SIZE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BI_ECAM_SIZE_MASK&#160;&#160;&#160;0x00070000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>ECAM size. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga6eaa13c68af6eb2ca12ae556f9e0769b">XAxiPcie_CfgInitialize()</a>, and <a class="el" href="group__axipcie__v3__0.html#ga75ca6a068024666c0199ea90d3ce4276">XAxiPcie_GetBridgeInfo()</a>.</p>

</div>
</div>
<a id="ga6e5ee78d2b39fa90a87fea37ed49d35a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6e5ee78d2b39fa90a87fea37ed49d35a">&#9670;&nbsp;</a></span>XAXIPCIE_BI_ECAM_SIZE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BI_ECAM_SIZE_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>PCIe ECAM Size Shift. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga6eaa13c68af6eb2ca12ae556f9e0769b">XAxiPcie_CfgInitialize()</a>, and <a class="el" href="group__axipcie__v3__0.html#ga75ca6a068024666c0199ea90d3ce4276">XAxiPcie_GetBridgeInfo()</a>.</p>

</div>
</div>
<a id="ga5c3e13956927d814f89b16d58bc87b71"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5c3e13956927d814f89b16d58bc87b71">&#9670;&nbsp;</a></span>XAXIPCIE_BI_GEN2_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BI_GEN2_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>PCIe Gen2 Speed Support Mask. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga75ca6a068024666c0199ea90d3ce4276">XAxiPcie_GetBridgeInfo()</a>.</p>

</div>
</div>
<a id="ga9f8bb352119692caff9e7851fe534498"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9f8bb352119692caff9e7851fe534498">&#9670;&nbsp;</a></span>XAXIPCIE_BI_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BI_OFFSET&#160;&#160;&#160;0x130</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Bridge Info Register. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga6eaa13c68af6eb2ca12ae556f9e0769b">XAxiPcie_CfgInitialize()</a>, and <a class="el" href="group__axipcie__v3__0.html#ga75ca6a068024666c0199ea90d3ce4276">XAxiPcie_GetBridgeInfo()</a>.</p>

</div>
</div>
<a id="gab624cf074fe8d343c15a086782e1150c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab624cf074fe8d343c15a086782e1150c">&#9670;&nbsp;</a></span>XAXIPCIE_BI_RP_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BI_RP_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>PCIe Root Port Support. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga75ca6a068024666c0199ea90d3ce4276">XAxiPcie_GetBridgeInfo()</a>.</p>

</div>
</div>
<a id="gae20709cf0062b87ed8689af2e8ee0a0a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae20709cf0062b87ed8689af2e8ee0a0a">&#9670;&nbsp;</a></span>XAXIPCIE_BI_RP_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BI_RP_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>PCIe Root Port Shift. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga75ca6a068024666c0199ea90d3ce4276">XAxiPcie_GetBridgeInfo()</a>.</p>

</div>
</div>
<a id="gaf8a11f087363d5ff57409bf45a597851"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf8a11f087363d5ff57409bf45a597851">&#9670;&nbsp;</a></span>XAXIPCIE_BL_BUS_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BL_BUS_MASK&#160;&#160;&#160;0x0000FF00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Requester ID Bus Number. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga77063428b5641d07910419770813c148">XAxiPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a id="gadc5afc68e0ece36131a9636a467ab327"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadc5afc68e0ece36131a9636a467ab327">&#9670;&nbsp;</a></span>XAXIPCIE_BL_BUS_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BL_BUS_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Requester ID Bus Number Shift Value. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga77063428b5641d07910419770813c148">XAxiPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a id="ga21a35da125896346b1a3219fe2dfcc93"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga21a35da125896346b1a3219fe2dfcc93">&#9670;&nbsp;</a></span>XAXIPCIE_BL_DEV_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BL_DEV_MASK&#160;&#160;&#160;0x000000F8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Requester ID Device Number. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga77063428b5641d07910419770813c148">XAxiPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a id="gaf0d3ce908be6f6c89a7212ddc42ba192"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf0d3ce908be6f6c89a7212ddc42ba192">&#9670;&nbsp;</a></span>XAXIPCIE_BL_DEV_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BL_DEV_SHIFT&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Requester ID Device Number Shift Value. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga77063428b5641d07910419770813c148">XAxiPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a id="ga269fecd1e2d8010e7b84e1339a5b2b94"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga269fecd1e2d8010e7b84e1339a5b2b94">&#9670;&nbsp;</a></span>XAXIPCIE_BL_FUNC_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BL_FUNC_MASK&#160;&#160;&#160;0x00000007</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Requester ID Function Number. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga77063428b5641d07910419770813c148">XAxiPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a id="gae8a758a6bb3b73be59a403a53ef97881"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae8a758a6bb3b73be59a403a53ef97881">&#9670;&nbsp;</a></span>XAXIPCIE_BL_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BL_OFFSET&#160;&#160;&#160;0x140</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Bus Location Register. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga77063428b5641d07910419770813c148">XAxiPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a id="gae40bca0b490429edd0c59df2f04dd595"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae40bca0b490429edd0c59df2f04dd595">&#9670;&nbsp;</a></span>XAXIPCIE_BL_PORT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BL_PORT_MASK&#160;&#160;&#160;0x00FF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Requester ID Port Number. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga77063428b5641d07910419770813c148">XAxiPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a id="ga7ef6bab98d1eba6156f808f92e39d7f2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7ef6bab98d1eba6156f808f92e39d7f2">&#9670;&nbsp;</a></span>XAXIPCIE_BL_PORT_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BL_PORT_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Requester ID Bus Number Shift Value. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga77063428b5641d07910419770813c148">XAxiPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a id="gabfb6e478c3f181fcec8e4918f9442296"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabfb6e478c3f181fcec8e4918f9442296">&#9670;&nbsp;</a></span>XAXIPCIE_BSC_ECAM_BUSY_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BSC_ECAM_BUSY_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>ECAM Busy Status. </p>

</div>
</div>
<a id="ga6a80436f1d395be5d4963d3f9d09f49c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6a80436f1d395be5d4963d3f9d09f49c">&#9670;&nbsp;</a></span>XAXIPCIE_BSC_GI_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BSC_GI_MASK&#160;&#160;&#160;0x00000100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Global Interrupt Disable. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#gaace3ba2f6c70cd207c9c65d92c634ee8">XAxiPcie_DisableGlobalInterrupt()</a>, and <a class="el" href="group__axipcie__v3__0.html#ga062809d176f81251886d5372c0714f7a">XAxiPcie_EnableGlobalInterrupt()</a>.</p>

</div>
</div>
<a id="ga92e6aa96f3a966ac3ac8b8b00bb770e6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga92e6aa96f3a966ac3ac8b8b00bb770e6">&#9670;&nbsp;</a></span>XAXIPCIE_BSC_GI_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BSC_GI_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Global Interrupt Disable Shift. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#gaace3ba2f6c70cd207c9c65d92c634ee8">XAxiPcie_DisableGlobalInterrupt()</a>, and <a class="el" href="group__axipcie__v3__0.html#ga062809d176f81251886d5372c0714f7a">XAxiPcie_EnableGlobalInterrupt()</a>.</p>

</div>
</div>
<a id="ga10e385edef3931106642fcf07d5a5fec"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga10e385edef3931106642fcf07d5a5fec">&#9670;&nbsp;</a></span>XAXIPCIE_BSC_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BSC_OFFSET&#160;&#160;&#160;0x134</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Bridge Status and Control Register. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#gaace3ba2f6c70cd207c9c65d92c634ee8">XAxiPcie_DisableGlobalInterrupt()</a>, and <a class="el" href="group__axipcie__v3__0.html#ga062809d176f81251886d5372c0714f7a">XAxiPcie_EnableGlobalInterrupt()</a>.</p>

</div>
</div>
<a id="ga7414766d143e8d20bf6ace5ca03548d8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7414766d143e8d20bf6ace5ca03548d8">&#9670;&nbsp;</a></span>XAXIPCIE_BSC_RO_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BSC_RO_MASK&#160;&#160;&#160;0x00020000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>RW Permissions to RO Registers. </p>

</div>
</div>
<a id="ga00ae2b626af9f11c9e3f9ccf4cbbd526"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga00ae2b626af9f11c9e3f9ccf4cbbd526">&#9670;&nbsp;</a></span>XAXIPCIE_BSC_RO_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BSC_RO_SHIFT&#160;&#160;&#160;17</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>RO as RW Shift. </p>

</div>
</div>
<a id="ga5d8d34b56c828dc51ee2bf7fe5876e6d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5d8d34b56c828dc51ee2bf7fe5876e6d">&#9670;&nbsp;</a></span>XAXIPCIE_BSC_RW1C_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BSC_RW1C_MASK&#160;&#160;&#160;0x00010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>RW Permissions to RW1C Registers. </p>

</div>
</div>
<a id="gac17ec341d56663eee8c61f478078e8e5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac17ec341d56663eee8c61f478078e8e5">&#9670;&nbsp;</a></span>XAXIPCIE_BSC_RW1C_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_BSC_RW1C_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>RW1C Shift. </p>

</div>
</div>
<a id="ga39ab6deaee9fe1e2ab734e85dc0fad5c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga39ab6deaee9fe1e2ab734e85dc0fad5c">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_BUS_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_BUS_MASK&#160;&#160;&#160;0x0FF00000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Bus Number Mask. </p>

</div>
</div>
<a id="gafe54d275930774f3ef2fa61861cc1047"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafe54d275930774f3ef2fa61861cc1047">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_BUS_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_BUS_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Bus Number Shift Value. </p>

</div>
</div>
<a id="ga188489525792d10a8892af78991ba828"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga188489525792d10a8892af78991ba828">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_BYT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_BYT_MASK&#160;&#160;&#160;0x00000003</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Byte Address Mask. </p>

</div>
</div>
<a id="ga9b1361bda2147f4bad36f800a61fa056"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9b1361bda2147f4bad36f800a61fa056">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_BYT_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_BYT_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Byte Offset Shift Value. </p>

</div>
</div>
<a id="ga7c530b27ed7392d44e98855cbf1582fe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7c530b27ed7392d44e98855cbf1582fe">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_DEV_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_DEV_MASK&#160;&#160;&#160;0x000F8000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Device Number Mask. </p>

</div>
</div>
<a id="gad8e00362272438c225cdf2bf5ee977e7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad8e00362272438c225cdf2bf5ee977e7">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_DEV_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_DEV_SHIFT&#160;&#160;&#160;15</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Device Number Shift Value. </p>

</div>
</div>
<a id="ga8b3e595d86874d13a20a84e998792ede"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8b3e595d86874d13a20a84e998792ede">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_FUN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_FUN_MASK&#160;&#160;&#160;0x00007000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Function Number Mask. </p>

</div>
</div>
<a id="gad6b61db832dff675f08c9f85b8d51027"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad6b61db832dff675f08c9f85b8d51027">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_FUN_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_FUN_SHIFT&#160;&#160;&#160;12</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Function Number Shift Value. </p>

</div>
</div>
<a id="gabbe43193c1a1f1b12a1e8e2910ffb02e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabbe43193c1a1f1b12a1e8e2910ffb02e">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_MASK&#160;&#160;&#160;0x0FFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Mask of all valid bits. </p>

</div>
</div>
<a id="gad62957cb703c4fdabd125b714ff3b113"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad62957cb703c4fdabd125b714ff3b113">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_REG_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_REG_MASK&#160;&#160;&#160;0x00000FFC</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Register Number Mask. </p>

</div>
</div>
<a id="ga40dade6a41bec5215be2714e28babe3b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga40dade6a41bec5215be2714e28babe3b">&#9670;&nbsp;</a></span>XAXIPCIE_ECAM_REG_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ECAM_REG_SHIFT&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Register Number Shift Value. </p>

</div>
</div>
<a id="ga846f47d9802bd878b3903c27673e4242"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga846f47d9802bd878b3903c27673e4242">&#9670;&nbsp;</a></span>XAXIPCIE_ID_CFG_COMPL_STATE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_CFG_COMPL_STATE_MASK&#160;&#160;&#160;0x000000E0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Cfg Completion Status Mask. </p>

</div>
</div>
<a id="ga5d2598bc52c54ea03294b1ddd915611a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5d2598bc52c54ea03294b1ddd915611a">&#9670;&nbsp;</a></span>XAXIPCIE_ID_CFG_TIMEOUT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_CFG_TIMEOUT_MASK&#160;&#160;&#160;0x00000100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Cfg timeout Mask. </p>

</div>
</div>
<a id="gaeb7c330e5d10623ceafc66dd08f149ea"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaeb7c330e5d10623ceafc66dd08f149ea">&#9670;&nbsp;</a></span>XAXIPCIE_ID_CLEAR_ALL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_CLEAR_ALL_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Mask of all Interrupts. </p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__ep__cdma__example_8c.html#a0305d38f6ee9ba0d3e2e545b96201ce3">PCIeEndPointInitialize()</a>, and <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

</div>
</div>
<a id="ga9d1319467ba4179502a8b4ef33bf4fe7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9d1319467ba4179502a8b4ef33bf4fe7">&#9670;&nbsp;</a></span>XAXIPCIE_ID_CMPL_ABT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_CMPL_ABT_MASK&#160;&#160;&#160;0x01000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Slave completion Abort Mask. </p>

</div>
</div>
<a id="gab0f88e6f4f242c99bd926d5db15cdb08"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab0f88e6f4f242c99bd926d5db15cdb08">&#9670;&nbsp;</a></span>XAXIPCIE_ID_CMPL_TIMEOUT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_CMPL_TIMEOUT_MASK&#160;&#160;&#160;0x00400000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Slave completion Time Mask. </p>

</div>
</div>
<a id="ga96cd9b31642245e067b4f746cd38a238"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga96cd9b31642245e067b4f746cd38a238">&#9670;&nbsp;</a></span>XAXIPCIE_ID_CORRECTABLE_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_CORRECTABLE_ERR_MASK&#160;&#160;&#160;0x00000200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Correctable Error Mask. </p>

</div>
</div>
<a id="ga2c5b6ef607113d639e16d43dd05b9405"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga2c5b6ef607113d639e16d43dd05b9405">&#9670;&nbsp;</a></span>XAXIPCIE_ID_DECODE_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_DECODE_ERR_MASK&#160;&#160;&#160;0x04000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Master Decode Error Interrupt Mask. </p>

</div>
</div>
<a id="gac24578f59c89ad7e659b6321259e005c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac24578f59c89ad7e659b6321259e005c">&#9670;&nbsp;</a></span>XAXIPCIE_ID_ECRC_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_ECRC_ERR_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Rx Packet CRC failed. </p>

</div>
</div>
<a id="ga193020c952d0d7ad38a3769887bd9d34"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga193020c952d0d7ad38a3769887bd9d34">&#9670;&nbsp;</a></span>XAXIPCIE_ID_FATAL_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_FATAL_ERR_MASK&#160;&#160;&#160;0x00000800</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Fatal Error Mask. </p>

</div>
</div>
<a id="gab7c127293e67e001584800088d052fee"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab7c127293e67e001584800088d052fee">&#9670;&nbsp;</a></span>XAXIPCIE_ID_HOT_RST_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_HOT_RST_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Hot Reset Mask. </p>

</div>
</div>
<a id="gae119f56dec65465b4438531840a8a759"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae119f56dec65465b4438531840a8a759">&#9670;&nbsp;</a></span>XAXIPCIE_ID_ILL_BURST_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_ILL_BURST_MASK&#160;&#160;&#160;0x02000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Slave Illegal Burst Mask. </p>

</div>
</div>
<a id="gacad1e038951dbef989a1d3b266af35c9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacad1e038951dbef989a1d3b266af35c9">&#9670;&nbsp;</a></span>XAXIPCIE_ID_INTX_INTERRUPT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_INTX_INTERRUPT&#160;&#160;&#160;0x00010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>INTX Interrupt. </p>

</div>
</div>
<a id="ga7d8d223d3881fc8e39d0d176974a5f97"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7d8d223d3881fc8e39d0d176974a5f97">&#9670;&nbsp;</a></span>XAXIPCIE_ID_LINK_DOWN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_LINK_DOWN_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Link Down Mask. </p>

</div>
</div>
<a id="ga96036ca77a405418f7e6da47d252f6c9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga96036ca77a405418f7e6da47d252f6c9">&#9670;&nbsp;</a></span>XAXIPCIE_ID_MASTER_EP_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_MASTER_EP_MASK&#160;&#160;&#160;0x10000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Master Error Poison Mask. </p>

</div>
</div>
<a id="gaf6f510e8eb119a47dd7f0ebc16801fac"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf6f510e8eb119a47dd7f0ebc16801fac">&#9670;&nbsp;</a></span>XAXIPCIE_ID_MSI_INTERRUPT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_MSI_INTERRUPT&#160;&#160;&#160;0x00020000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>MSI Interrupt. </p>

</div>
</div>
<a id="ga79e63cd543f66440b3b227807636ee90"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga79e63cd543f66440b3b227807636ee90">&#9670;&nbsp;</a></span>XAXIPCIE_ID_NONFATAL_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_NONFATAL_ERR_MASK&#160;&#160;&#160;0x00000400</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Non-Fatal Error Mask. </p>

</div>
</div>
<a id="gaf4ee25f8cd866c3c4c79bd9f1a784a7c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf4ee25f8cd866c3c4c79bd9f1a784a7c">&#9670;&nbsp;</a></span>XAXIPCIE_ID_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_OFFSET&#160;&#160;&#160;0x138</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Interrupt Decode Register. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#gabdf66d0cb481a5eea62e1f98e71d9520">XAxiPcie_ClearPendingInterrupts()</a>, and <a class="el" href="group__axipcie__v3__0.html#gaec39c65db1aeac38798a250a25298208">XAxiPcie_GetPendingInterrupts()</a>.</p>

</div>
</div>
<a id="gaa6dd437acd81c0284bfd1ed1563cfbb7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa6dd437acd81c0284bfd1ed1563cfbb7">&#9670;&nbsp;</a></span>XAXIPCIE_ID_SLAVE_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_SLAVE_ERR_MASK&#160;&#160;&#160;0x08000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Master Slave Error Interrupt Mask. </p>

</div>
</div>
<a id="ga1298f6ace7fb8944f15181c960a90beb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1298f6ace7fb8944f15181c960a90beb">&#9670;&nbsp;</a></span>XAXIPCIE_ID_SLV_EP_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_SLV_EP_MASK&#160;&#160;&#160;0x00800000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Slave Error Poison Mask. </p>

</div>
</div>
<a id="gac12ef40af613a60dd229b11010e850ef"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac12ef40af613a60dd229b11010e850ef">&#9670;&nbsp;</a></span>XAXIPCIE_ID_STR_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_STR_ERR_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Streaming Error Mask. </p>

</div>
</div>
<a id="ga16dc91d210fc5079a0c4aa475946818f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga16dc91d210fc5079a0c4aa475946818f">&#9670;&nbsp;</a></span>XAXIPCIE_ID_UNEXP_CMPL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_UNEXP_CMPL_MASK&#160;&#160;&#160;0x00200000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Slave Unexpected Completion Mask. </p>

</div>
</div>
<a id="gaa428513b46014681de2bf99c3cfac84e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa428513b46014681de2bf99c3cfac84e">&#9670;&nbsp;</a></span>XAXIPCIE_ID_UNSUPP_CMPL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_ID_UNSUPP_CMPL_MASK&#160;&#160;&#160;0x00100000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Slave Unsupported Request Mask. </p>

</div>
</div>
<a id="ga1da6c8b6280b6726d8ac6178bf11af15"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1da6c8b6280b6726d8ac6178bf11af15">&#9670;&nbsp;</a></span>XAXIPCIE_IM_DISABLE_ALL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_IM_DISABLE_ALL_MASK&#160;&#160;&#160;0x00000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Disable All Interrupts. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga6eaa13c68af6eb2ca12ae556f9e0769b">XAxiPcie_CfgInitialize()</a>.</p>

</div>
</div>
<a id="ga40d5e3c669642af8441aed4d5ad23ee2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga40d5e3c669642af8441aed4d5ad23ee2">&#9670;&nbsp;</a></span>XAXIPCIE_IM_ENABLE_ALL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_IM_ENABLE_ALL_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Enable All Interrupts. </p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__ep__cdma__example_8c.html#a0305d38f6ee9ba0d3e2e545b96201ce3">PCIeEndPointInitialize()</a>, and <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

</div>
</div>
<a id="gad798e4bbf2fc4fe5135dfa56fac31399"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad798e4bbf2fc4fe5135dfa56fac31399">&#9670;&nbsp;</a></span>XAXIPCIE_IM_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_IM_OFFSET&#160;&#160;&#160;0x13C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Interrupt Mask Register. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#gae238cf115bd039e0f7228e385c893aad">XAxiPcie_DisableInterrupts()</a>, <a class="el" href="group__axipcie__v3__0.html#ga22a95261655e78a944d1a2462031da57">XAxiPcie_EnableInterrupts()</a>, and <a class="el" href="group__axipcie__v3__0.html#gae118e9d7fd6b78ca0b8d4fd6694f9808">XAxiPcie_GetEnabledInterrupts()</a>.</p>

</div>
</div>
<a id="ga4eff130db70eebadac90b43cbd2561fa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4eff130db70eebadac90b43cbd2561fa">&#9670;&nbsp;</a></span>XAxiPcie_IsEcamBusy</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiPcie_IsEcamBusy</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div><div class="line">        <a class="code" href="group__axipcie__v3__0.html#ga10e385edef3931106642fcf07d5a5fec">XAXIPCIE_BSC_OFFSET</a>) &amp; <a class="code" href="group__axipcie__v3__0.html#gabfb6e478c3f181fcec8e4918f9442296">XAXIPCIE_BSC_ECAM_BUSY_MASK</a>) ? TRUE : FALSE</div><div class="ttc" id="group__axipcie__v3__0_html_gabfb6e478c3f181fcec8e4918f9442296"><div class="ttname"><a href="group__axipcie__v3__0.html#gabfb6e478c3f181fcec8e4918f9442296">XAXIPCIE_BSC_ECAM_BUSY_MASK</a></div><div class="ttdeci">#define XAXIPCIE_BSC_ECAM_BUSY_MASK</div><div class="ttdoc">ECAM Busy Status. </div><div class="ttdef"><b>Definition:</b> xaxipcie_hw.h:361</div></div>
<div class="ttc" id="group__axipcie__v3__0_html_gab5e38a3a5815c463c52461a8f7f52b75"><div class="ttname"><a href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a></div><div class="ttdeci">#define XAxiPcie_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Macro to read register. </div><div class="ttdef"><b>Definition:</b> xaxipcie_hw.h:811</div></div>
<div class="ttc" id="group__axipcie__v3__0_html_ga10e385edef3931106642fcf07d5a5fec"><div class="ttname"><a href="group__axipcie__v3__0.html#ga10e385edef3931106642fcf07d5a5fec">XAXIPCIE_BSC_OFFSET</a></div><div class="ttdeci">#define XAXIPCIE_BSC_OFFSET</div><div class="ttdoc">Bridge Status and Control Register. </div><div class="ttdef"><b>Definition:</b> xaxipcie_hw.h:106</div></div>
</div><!-- fragment -->
<p>Check whether ECAM is busy or not. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE if ECAM is busy</li>
<li>FALSE if ECAM is idel</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex </dd></dl>

</div>
</div>
<a id="ga08e3f639ed3ca042d429630fec260654"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga08e3f639ed3ca042d429630fec260654">&#9670;&nbsp;</a></span>XAxiPcie_IsLinkUp</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiPcie_IsLinkUp</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress,    \</div><div class="line">        <a class="code" href="group__axipcie__v3__0.html#ga84f89f155288e2a5de41a09bdf5d8672">XAXIPCIE_PHYSC_OFFSET</a>) &amp; <a class="code" href="group__axipcie__v3__0.html#ga1b1c63c3222b1c3585b7b7ba73a46db8">XAXIPCIE_PHYSC_LINK_UP_MASK</a>) ? TRUE : FALSE</div><div class="ttc" id="group__axipcie__v3__0_html_ga1b1c63c3222b1c3585b7b7ba73a46db8"><div class="ttname"><a href="group__axipcie__v3__0.html#ga1b1c63c3222b1c3585b7b7ba73a46db8">XAXIPCIE_PHYSC_LINK_UP_MASK</a></div><div class="ttdeci">#define XAXIPCIE_PHYSC_LINK_UP_MASK</div><div class="ttdoc">Link Up Status Mask. </div><div class="ttdef"><b>Definition:</b> xaxipcie_hw.h:508</div></div>
<div class="ttc" id="group__axipcie__v3__0_html_gab5e38a3a5815c463c52461a8f7f52b75"><div class="ttname"><a href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a></div><div class="ttdeci">#define XAxiPcie_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Macro to read register. </div><div class="ttdef"><b>Definition:</b> xaxipcie_hw.h:811</div></div>
<div class="ttc" id="group__axipcie__v3__0_html_ga84f89f155288e2a5de41a09bdf5d8672"><div class="ttname"><a href="group__axipcie__v3__0.html#ga84f89f155288e2a5de41a09bdf5d8672">XAXIPCIE_PHYSC_OFFSET</a></div><div class="ttdeci">#define XAXIPCIE_PHYSC_OFFSET</div><div class="ttdoc">Physical status and Control Register. </div><div class="ttdef"><b>Definition:</b> xaxipcie_hw.h:132</div></div>
</div><!-- fragment -->
<p>Check whether link is up or not. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE if link is up</li>
<li>FALSE if link is down</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p class="reference">Referenced by <a class="el" href="xaxipcie__ep__cdma__example_8c.html#a0305d38f6ee9ba0d3e2e545b96201ce3">PCIeEndPointInitialize()</a>, and <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

</div>
</div>
<a id="ga7cecef23e8a28935226e7dc9815390c0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7cecef23e8a28935226e7dc9815390c0">&#9670;&nbsp;</a></span>XAXIPCIE_PCIE_CORE_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PCIE_CORE_OFFSET&#160;&#160;&#160;0x000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>PCI Express hard core configuration register offset. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#gad9494095b9350f455af9e7da5375d522">XAxiPcie_ReadLocalConfigSpace()</a>.</p>

</div>
</div>
<a id="gaaf6ed374b48c1d8d127a3cc0fa1dd082"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaaf6ed374b48c1d8d127a3cc0fa1dd082">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_DLA_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_DLA_MASK&#160;&#160;&#160;0x00080000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Directed Link Change change to reliability or Autonomus Mask. </p>

</div>
</div>
<a id="ga39556f83d4e88ec7783db2826ce5303d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga39556f83d4e88ec7783db2826ce5303d">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_DLA_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_DLA_SHIFT&#160;&#160;&#160;19</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Directed Link change to reliability or Autonomus Shift. </p>

</div>
</div>
<a id="gaf3422457e569985908990b125ded1b5f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf3422457e569985908990b125ded1b5f">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_DLC_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_DLC_MASK&#160;&#160;&#160;0x00300000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Directed Link change Mask. </p>

</div>
</div>
<a id="gaabf018637b6aa1ca5b7ca4657ed2583a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaabf018637b6aa1ca5b7ca4657ed2583a">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_DLC_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_DLC_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Directed Link change Shift. </p>

</div>
</div>
<a id="ga238bcf6752996345861f9e958ee5bddc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga238bcf6752996345861f9e958ee5bddc">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_DLW_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_DLW_MASK&#160;&#160;&#160;0x00030000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Directed Link Width to change Mask. </p>

</div>
</div>
<a id="ga7e9344be85c4daabbe33825ec565e348"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7e9344be85c4daabbe33825ec565e348">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_DLW_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_DLW_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Directed Link Width to change Shift. </p>

</div>
</div>
<a id="ga04fd250e831f12d2274e81fc11f8544a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga04fd250e831f12d2274e81fc11f8544a">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_DLWS_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_DLWS_MASK&#160;&#160;&#160;0x00040000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Directed Link Width Speed to change Mask. </p>

</div>
</div>
<a id="gab4aba0340f18918d3aa073dfe631724c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab4aba0340f18918d3aa073dfe631724c">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_DLWS_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_DLWS_SHIFT&#160;&#160;&#160;18</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Directed Link Width Speed to change Shift. </p>

</div>
</div>
<a id="ga1d873d3497027ad74b8d0240a28ab11d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1d873d3497027ad74b8d0240a28ab11d">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_LANE_REV_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_LANE_REV_MASK&#160;&#160;&#160;0x00000600</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Lane Reversal Mask. </p>

</div>
</div>
<a id="gad478317d1ca0eae5e32d87e51bbb0a92"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad478317d1ca0eae5e32d87e51bbb0a92">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_LANE_REV_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_LANE_REV_SHIFT&#160;&#160;&#160;9</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Lane Reversal Shift. </p>

</div>
</div>
<a id="ga1238d2aba155c18a5ce7b45d2a1cbe39"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1238d2aba155c18a5ce7b45d2a1cbe39">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_LINK_RATE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_LINK_RATE_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Link Rate. </p>

</div>
</div>
<a id="ga1b1c63c3222b1c3585b7b7ba73a46db8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1b1c63c3222b1c3585b7b7ba73a46db8">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_LINK_UP_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_LINK_UP_MASK&#160;&#160;&#160;0x00000800</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Link Up Status Mask. </p>

</div>
</div>
<a id="ga6b51f3442219824eb75fc8ff3cfe1660"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6b51f3442219824eb75fc8ff3cfe1660">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_LINK_UP_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_LINK_UP_SHIFT&#160;&#160;&#160;11</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Link Up Status Shift. </p>

</div>
</div>
<a id="ga1afe809e17692a8fac45d860ac99c4d3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1afe809e17692a8fac45d860ac99c4d3">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_LINK_WIDTH_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_LINK_WIDTH_MASK&#160;&#160;&#160;0x00000006</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Link Width Mask. </p>

</div>
</div>
<a id="gaef8ab25bd7ab6a989ddc832c2c50c2e4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaef8ab25bd7ab6a989ddc832c2c50c2e4">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_LINK_WIDTH_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_LINK_WIDTH_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Link Status Shift. </p>

</div>
</div>
<a id="ga83dbe369846939579a0dd3d74476bcb7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga83dbe369846939579a0dd3d74476bcb7">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_LTSSM_STATE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_LTSSM_STATE_MASK&#160;&#160;&#160;0x000001F8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>LTSSM State Mask. </p>

</div>
</div>
<a id="ga41728830bc4094a6044ea629c4699201"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga41728830bc4094a6044ea629c4699201">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_LTSSM_STATE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_LTSSM_STATE_SHIFT&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>LTSSM State Shift. </p>

</div>
</div>
<a id="ga84f89f155288e2a5de41a09bdf5d8672"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga84f89f155288e2a5de41a09bdf5d8672">&#9670;&nbsp;</a></span>XAXIPCIE_PHYSC_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_PHYSC_OFFSET&#160;&#160;&#160;0x144</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Physical status and Control Register. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga372301905fec6833c06320fb45261cd7">XAxiPcie_GetPhyStatusCtrl()</a>.</p>

</div>
</div>
<a id="gab5e38a3a5815c463c52461a8f7f52b75"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab5e38a3a5815c463c52461a8f7f52b75">&#9670;&nbsp;</a></span>XAxiPcie_ReadReg</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiPcie_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Macro to read register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the PCIe. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75" title="Macro to read register. ">XAxiPcie_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga6eaa13c68af6eb2ca12ae556f9e0769b">XAxiPcie_CfgInitialize()</a>, <a class="el" href="group__axipcie__v3__0.html#gabdf66d0cb481a5eea62e1f98e71d9520">XAxiPcie_ClearPendingInterrupts()</a>, <a class="el" href="group__axipcie__v3__0.html#gaace3ba2f6c70cd207c9c65d92c634ee8">XAxiPcie_DisableGlobalInterrupt()</a>, <a class="el" href="group__axipcie__v3__0.html#gae238cf115bd039e0f7228e385c893aad">XAxiPcie_DisableInterrupts()</a>, <a class="el" href="group__axipcie__v3__0.html#ga062809d176f81251886d5372c0714f7a">XAxiPcie_EnableGlobalInterrupt()</a>, <a class="el" href="group__axipcie__v3__0.html#ga22a95261655e78a944d1a2462031da57">XAxiPcie_EnableInterrupts()</a>, <a class="el" href="group__axipcie__v3__0.html#ga75ca6a068024666c0199ea90d3ce4276">XAxiPcie_GetBridgeInfo()</a>, <a class="el" href="group__axipcie__v3__0.html#gae118e9d7fd6b78ca0b8d4fd6694f9808">XAxiPcie_GetEnabledInterrupts()</a>, <a class="el" href="group__axipcie__v3__0.html#ga19d8a1973231160bdd518b1c62bda3d4">XAxiPcie_GetLocalBusBar2PcieBar()</a>, <a class="el" href="group__axipcie__v3__0.html#gaec39c65db1aeac38798a250a25298208">XAxiPcie_GetPendingInterrupts()</a>, <a class="el" href="group__axipcie__v3__0.html#ga372301905fec6833c06320fb45261cd7">XAxiPcie_GetPhyStatusCtrl()</a>, <a class="el" href="group__axipcie__v3__0.html#ga77063428b5641d07910419770813c148">XAxiPcie_GetRequesterId()</a>, <a class="el" href="group__axipcie__v3__0.html#ga745d2811e366fbe0e5499cfef90adbcc">XAxiPcie_GetVsecCapability()</a>, <a class="el" href="group__axipcie__v3__0.html#gaa26f5255cb42e55351c7cb802f71d56c">XAxiPcie_GetVsecHeader()</a>, and <a class="el" href="group__axipcie__v3__0.html#gad9494095b9350f455af9e7da5375d522">XAxiPcie_ReadLocalConfigSpace()</a>.</p>

</div>
</div>
<a id="ga76dd5672aa49d1675193c515ee99275e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga76dd5672aa49d1675193c515ee99275e">&#9670;&nbsp;</a></span>XAXIPCIE_RPEFR_ERR_TYPE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPEFR_ERR_TYPE_MASK&#160;&#160;&#160;0x00030000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Type of Error. </p>

</div>
</div>
<a id="ga285c4d376d023b3b9df54754606808df"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga285c4d376d023b3b9df54754606808df">&#9670;&nbsp;</a></span>XAXIPCIE_RPEFR_ERR_TYPE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPEFR_ERR_TYPE_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Type of Error Shift. </p>

</div>
</div>
<a id="ga0d7406f32c476e78d25f92fab2bbb30b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0d7406f32c476e78d25f92fab2bbb30b">&#9670;&nbsp;</a></span>XAXIPCIE_RPEFR_ERR_VALID_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPEFR_ERR_VALID_MASK&#160;&#160;&#160;0x00040000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Error Read Succeeded Status. </p>

</div>
</div>
<a id="gacb9ed69607f6da66cc0501f4f18bb732"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacb9ed69607f6da66cc0501f4f18bb732">&#9670;&nbsp;</a></span>XAXIPCIE_RPEFR_ERR_VALID_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPEFR_ERR_VALID_SHIFT&#160;&#160;&#160;18</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Error Read Succeeded Status Shift. </p>

</div>
</div>
<a id="ga8e3c116efe4ad6fc7c0d87a4fdea9dab"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8e3c116efe4ad6fc7c0d87a4fdea9dab">&#9670;&nbsp;</a></span>XAXIPCIE_RPEFR_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPEFR_OFFSET&#160;&#160;&#160;0x154</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Error FIFO Read Register. </p>

</div>
</div>
<a id="ga4e82350a3eb45f3f8a61351de81d39c9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4e82350a3eb45f3f8a61351de81d39c9">&#9670;&nbsp;</a></span>XAXIPCIE_RPEFR_REQ_ID_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPEFR_REQ_ID_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Requester of Error Msg. </p>

</div>
</div>
<a id="gaa573753049273f1ece6a4b24917d2b05"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa573753049273f1ece6a4b24917d2b05">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR1_INTR_ASSERT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR1_INTR_ASSERT_MASK&#160;&#160;&#160;0x20000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Whether Interrupt INTx is asserted. </p>

</div>
</div>
<a id="gaaf545ca193095942641304d55ce7e416"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaaf545ca193095942641304d55ce7e416">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR1_INTR_LINE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR1_INTR_LINE_MASK&#160;&#160;&#160;0x18000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Intr Line Mask. </p>

</div>
</div>
<a id="gaf9a5f8ec646e50bdc31887a508f50fc5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf9a5f8ec646e50bdc31887a508f50fc5">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR1_INTR_VALID_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR1_INTR_VALID_MASK&#160;&#160;&#160;0x80000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Interrupt Read Succeeded Status. </p>

</div>
</div>
<a id="gabdd55507fa3a696908e3d31abe7ff1e6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabdd55507fa3a696908e3d31abe7ff1e6">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR1_INTR_VALID_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR1_INTR_VALID_SHIFT&#160;&#160;&#160;31</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Interrupt Read Valid Shift. </p>

</div>
</div>
<a id="gad2a9c673eaa9cdb18e3ac3788fcb834d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad2a9c673eaa9cdb18e3ac3788fcb834d">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR1_MSI_ADDR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR1_MSI_ADDR_MASK&#160;&#160;&#160;0x07FF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>MSI Address. </p>

</div>
</div>
<a id="ga71868428e591d5f59fd40151da6d3aa5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga71868428e591d5f59fd40151da6d3aa5">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR1_MSI_ADDR_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR1_MSI_ADDR_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>MSI Address Shift. </p>

</div>
</div>
<a id="ga9d9b70e72dbf4e3db706b28f5f749e74"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9d9b70e72dbf4e3db706b28f5f749e74">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR1_MSIINTR_VALID_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR1_MSIINTR_VALID_MASK&#160;&#160;&#160;0x40000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Whether Interrupt is MSI or INTx. </p>

</div>
</div>
<a id="ga0465365bbae94b36de39aceeb580cdd1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0465365bbae94b36de39aceeb580cdd1">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR1_MSIINTR_VALID_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR1_MSIINTR_VALID_SHIFT&#160;&#160;&#160;30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>MSI/INTx Interrupt Shift. </p>

</div>
</div>
<a id="gad61ae31bb34ed3e02243c5d74ac75afa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad61ae31bb34ed3e02243c5d74ac75afa">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR1_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR1_OFFSET&#160;&#160;&#160;0x158</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Interrupt FIFO Read1 Register. </p>

</div>
</div>
<a id="ga477d9111e2c1e6932b00b658cda9df01"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga477d9111e2c1e6932b00b658cda9df01">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR1_REQ_ID_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR1_REQ_ID_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Requester Id of Interrupt Message. </p>

</div>
</div>
<a id="gaaf6ce74eb3d24d535f2c399330c27af9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaaf6ce74eb3d24d535f2c399330c27af9">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR2_MSG_DATA_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR2_MSG_DATA_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Pay Load for MSI Message. </p>

</div>
</div>
<a id="ga92a83142f665f34045a5235732060c47"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga92a83142f665f34045a5235732060c47">&#9670;&nbsp;</a></span>XAXIPCIE_RPIFR2_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPIFR2_OFFSET&#160;&#160;&#160;0x15C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Interrupt FIFO Read2 Register. </p>

</div>
</div>
<a id="gac25094bce1e85b534dc154222a7d83a3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac25094bce1e85b534dc154222a7d83a3">&#9670;&nbsp;</a></span>XAXIPCIE_RPMSIB_LOWER_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPMSIB_LOWER_MASK&#160;&#160;&#160;0xFFFFF000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Lower 32 bits of 64 bit MSI Base Address. </p>

</div>
</div>
<a id="ga7fff8ece26635ba08deb9dd05f6283a1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7fff8ece26635ba08deb9dd05f6283a1">&#9670;&nbsp;</a></span>XAXIPCIE_RPMSIB_LOWER_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPMSIB_LOWER_OFFSET&#160;&#160;&#160;0x150</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port MSI Base 2 Register Lower 32 bits from 64 bit address are written. </p>

</div>
</div>
<a id="ga6b8ab2e2dd878a06c3fec3bef2612f88"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6b8ab2e2dd878a06c3fec3bef2612f88">&#9670;&nbsp;</a></span>XAXIPCIE_RPMSIB_UPPER_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPMSIB_UPPER_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Upper 32 bits of 64 bit MSI Base Address. </p>

</div>
</div>
<a id="ga5b498715d2bbafc1a81fea7abd853f29"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5b498715d2bbafc1a81fea7abd853f29">&#9670;&nbsp;</a></span>XAXIPCIE_RPMSIB_UPPER_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPMSIB_UPPER_OFFSET&#160;&#160;&#160;0x14C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port MSI Base 1 Register Upper 32 bits from 64 bit address are written. </p>

</div>
</div>
<a id="ga7239a578a5e3bbf80fac05bab9a841aa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7239a578a5e3bbf80fac05bab9a841aa">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_BRIDGE_ENABLE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_BRIDGE_ENABLE_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Bridge Enable Mask. </p>

</div>
</div>
<a id="gaae47e36bef3304c2ed171d5c4263b356"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaae47e36bef3304c2ed171d5c4263b356">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_COMP_TIMEOUT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_COMP_TIMEOUT_MASK&#160;&#160;&#160;0x0FF00000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Completion Timeout. </p>

</div>
</div>
<a id="ga5bd566eee0347d55e43ce6c803fd9ea6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5bd566eee0347d55e43ce6c803fd9ea6">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_COMP_TIMEOUT_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_COMP_TIMEOUT_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Completion Timeout Shift. </p>

</div>
</div>
<a id="ga306dded24643ad2589e7773a278198c2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga306dded24643ad2589e7773a278198c2">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_MASK&#160;&#160;&#160;0x00010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Error FIFO Not Empty. </p>

</div>
</div>
<a id="gae31c1b6a918ba904627c85e1b1e90cd7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae31c1b6a918ba904627c85e1b1e90cd7">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Error FIFO Empty Shift. </p>

</div>
</div>
<a id="gaad476109c1b88e734cd0c487551ecd38"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaad476109c1b88e734cd0c487551ecd38">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_MASK&#160;&#160;&#160;0x00020000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Error FIFO Overflow. </p>

</div>
</div>
<a id="ga4c13191564e035b1f82bd03a2618ae68"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4c13191564e035b1f82bd03a2618ae68">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_SHIFT&#160;&#160;&#160;17</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Error FIFO Overflow Shift. </p>

</div>
</div>
<a id="gad174b729ea9da546195a3e35b5306296"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad174b729ea9da546195a3e35b5306296">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_MASK&#160;&#160;&#160;0x00040000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Interrupt FIFO Not Empty. </p>

</div>
</div>
<a id="gac928e2b08d55a229e1bcb3064c420152"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac928e2b08d55a229e1bcb3064c420152">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_SHIFT&#160;&#160;&#160;18</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Interrupt FIFO Empty Shift. </p>

</div>
</div>
<a id="gae7e2cf8f647b545ca89191d281d28500"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae7e2cf8f647b545ca89191d281d28500">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_MASK&#160;&#160;&#160;0x00080000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Interrupt FIFO Overflow. </p>

</div>
</div>
<a id="ga487c2d600b1745aeda32d7987c08ba79"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga487c2d600b1745aeda32d7987c08ba79">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_SHIFT&#160;&#160;&#160;19</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Interrupt FIFO Overflow Shift. </p>

</div>
</div>
<a id="ga727eba08077bad1923e3ff44e5522110"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga727eba08077bad1923e3ff44e5522110">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_MASK&#160;&#160;&#160;0x0FFF0001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Register mask. </p>

</div>
</div>
<a id="gafb8cd2a16037d697cf4a5af55506af44"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafb8cd2a16037d697cf4a5af55506af44">&#9670;&nbsp;</a></span>XAXIPCIE_RPSC_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_RPSC_OFFSET&#160;&#160;&#160;0x148</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Root Port Status &amp; Control Register. </p>

</div>
</div>
<a id="ga3950d5b04a69dcbc2e2c5711cb657745"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3950d5b04a69dcbc2e2c5711cb657745">&#9670;&nbsp;</a></span>XAXIPCIE_UP_CONFIG_CAPABLE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_UP_CONFIG_CAPABLE&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Up Config Capable. </p>

</div>
</div>
<a id="ga7e5fb7cdef729030bf31e9c3651253b1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7e5fb7cdef729030bf31e9c3651253b1">&#9670;&nbsp;</a></span>XAXIPCIE_VSEC1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSEC1&#160;&#160;&#160;0x00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>First VSEC Register. </p>

</div>
</div>
<a id="ga08b7198f8d99e2f00b912ae94f25d088"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga08b7198f8d99e2f00b912ae94f25d088">&#9670;&nbsp;</a></span>XAXIPCIE_VSEC2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSEC2&#160;&#160;&#160;0x01</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Second VSEC Register. </p>

</div>
</div>
<a id="gabd84445ebce4bfcb25ca5b75799bbba5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabd84445ebce4bfcb25ca5b75799bbba5">&#9670;&nbsp;</a></span>XAXIPCIE_VSECC_ID_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECC_ID_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Vsec capability Id. </p>

</div>
</div>
<a id="gaca2f85036ff847a8f3c9def6d402bfe3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaca2f85036ff847a8f3c9def6d402bfe3">&#9670;&nbsp;</a></span>XAXIPCIE_VSECC_NEXT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECC_NEXT_MASK&#160;&#160;&#160;0xFFF00000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Offset to next capability. </p>

</div>
</div>
<a id="ga4ea49e123b5a60e753034437e748a455"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4ea49e123b5a60e753034437e748a455">&#9670;&nbsp;</a></span>XAXIPCIE_VSECC_NEXT_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECC_NEXT_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Next capability offset shift. </p>

</div>
</div>
<a id="gaf01ed785ab64d6c124437532ece335ce"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf01ed785ab64d6c124437532ece335ce">&#9670;&nbsp;</a></span>XAXIPCIE_VSECC_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECC_OFFSET&#160;&#160;&#160;0x128</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>VSEC Capability Register. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#ga745d2811e366fbe0e5499cfef90adbcc">XAxiPcie_GetVsecCapability()</a>.</p>

</div>
</div>
<a id="ga8724baa412ffd4bd593fd67c2928c3a1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8724baa412ffd4bd593fd67c2928c3a1">&#9670;&nbsp;</a></span>XAXIPCIE_VSECC_VER_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECC_VER_MASK&#160;&#160;&#160;0x000F0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Version of capability Structure. </p>

</div>
</div>
<a id="gab791a04d374dfc7d88d5e3c817126b8f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab791a04d374dfc7d88d5e3c817126b8f">&#9670;&nbsp;</a></span>XAXIPCIE_VSECC_VER_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECC_VER_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>VSEC Version shift. </p>

</div>
</div>
<a id="gafd846b29aae82d036fc3ea66ef65596f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafd846b29aae82d036fc3ea66ef65596f">&#9670;&nbsp;</a></span>XAXIPCIE_VSECH_ID_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECH_ID_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Vsec structure Id. </p>

</div>
</div>
<a id="gaed6b0e6cd2817f7c5c69c3290833447e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaed6b0e6cd2817f7c5c69c3290833447e">&#9670;&nbsp;</a></span>XAXIPCIE_VSECH_LEN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECH_LEN_MASK&#160;&#160;&#160;0xFFF00000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Length of Vsec capability structure. </p>

</div>
</div>
<a id="gaa6e2e6e5e712fa8b44077688caee37d1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa6e2e6e5e712fa8b44077688caee37d1">&#9670;&nbsp;</a></span>XAXIPCIE_VSECH_LEN_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECH_LEN_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Vsec length shift. </p>

</div>
</div>
<a id="gab99ecd675b55df50a385fc7b429d38e4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab99ecd675b55df50a385fc7b429d38e4">&#9670;&nbsp;</a></span>XAXIPCIE_VSECH_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECH_OFFSET&#160;&#160;&#160;0x12C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>VSEC Header Register. </p>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#gaa26f5255cb42e55351c7cb802f71d56c">XAxiPcie_GetVsecHeader()</a>.</p>

</div>
</div>
<a id="ga94c0af68259b5949d6c003dd85d46b2d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga94c0af68259b5949d6c003dd85d46b2d">&#9670;&nbsp;</a></span>XAXIPCIE_VSECH_REV_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECH_REV_MASK&#160;&#160;&#160;0x000F0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Vsec header version. </p>

</div>
</div>
<a id="ga591f34e1c213bb45aba99629c71b565b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga591f34e1c213bb45aba99629c71b565b">&#9670;&nbsp;</a></span>XAXIPCIE_VSECH_REV_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIPCIE_VSECH_REV_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Vsec version shift. </p>

</div>
</div>
<a id="gaf3312e39c24adeb6a06a7408a68a1e80"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf3312e39c24adeb6a06a7408a68a1e80">&#9670;&nbsp;</a></span>XAxiPcie_WriteReg</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiPcie_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie__hw_8h.html">xaxipcie_hw.h</a>&gt;</code></p>

<p>Macro to write register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the PCIe. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset. </td></tr>
    <tr><td class="paramname">Data</td><td>is the data to write.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XAxiPcie_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axipcie__v3__0.html#gabdf66d0cb481a5eea62e1f98e71d9520">XAxiPcie_ClearPendingInterrupts()</a>, <a class="el" href="group__axipcie__v3__0.html#gaace3ba2f6c70cd207c9c65d92c634ee8">XAxiPcie_DisableGlobalInterrupt()</a>, <a class="el" href="group__axipcie__v3__0.html#gae238cf115bd039e0f7228e385c893aad">XAxiPcie_DisableInterrupts()</a>, <a class="el" href="group__axipcie__v3__0.html#ga062809d176f81251886d5372c0714f7a">XAxiPcie_EnableGlobalInterrupt()</a>, <a class="el" href="group__axipcie__v3__0.html#ga22a95261655e78a944d1a2462031da57">XAxiPcie_EnableInterrupts()</a>, and <a class="el" href="group__axipcie__v3__0.html#ga51ee29d03fbefc82b9208f46a12d5a06">XAxiPcie_SetLocalBusBar2PcieBar()</a>.</p>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a id="ga6eaa13c68af6eb2ca12ae556f9e0769b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6eaa13c68af6eb2ca12ae556f9e0769b">&#9670;&nbsp;</a></span>XAxiPcie_CfgInitialize()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">int XAxiPcie_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie___config.html">XAxiPcie_Config</a> *&#160;</td>
          <td class="paramname"><em>CfgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddress</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Initialize the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance provided by the caller based on the given Config structure. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on.The memory of the pointer references must be pre-allocated by the caller. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>is the device configuration structure containing required HW build data. </td></tr>
    <tr><td class="paramname">EffectiveAddress</td><td>is the Physical address of the hardware in a Virtual Memory operating system environment.It is the Base Address in a stand alone environment.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><pre class="fragment">            - XST_SUCCESS Initialization was successful.
</pre></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="struct_x_axi_pcie.html#a75ec06e432dfea5967d2912b2af901b0">XAxiPcie::MaxNumOfBuses</a>, <a class="el" href="group__axipcie__v3__0.html#ga2d99e62d5248da57465cd526eaf9cb01">XAXIPCIE_BI_ECAM_SIZE_MASK</a>, <a class="el" href="group__axipcie__v3__0.html#ga6e5ee78d2b39fa90a87fea37ed49d35a">XAXIPCIE_BI_ECAM_SIZE_SHIFT</a>, <a class="el" href="group__axipcie__v3__0.html#ga9f8bb352119692caff9e7851fe534498">XAXIPCIE_BI_OFFSET</a>, <a class="el" href="group__axipcie__v3__0.html#gae238cf115bd039e0f7228e385c893aad">XAxiPcie_DisableInterrupts()</a>, <a class="el" href="group__axipcie__v3__0.html#ga1da6c8b6280b6726d8ac6178bf11af15">XAXIPCIE_IM_DISABLE_ALL_MASK</a>, and <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__ep__cdma__example_8c.html#a0305d38f6ee9ba0d3e2e545b96201ce3">PCIeEndPointInitialize()</a>, and <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gabdf66d0cb481a5eea62e1f98e71d9520">&#9670;&nbsp;</a></span>XAxiPcie_ClearPendingInterrupts()</h2>

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<div class="memproto">
      <table class="memname">
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          <td class="memname">void XAxiPcie_ClearPendingInterrupts </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>ClearMask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Clear the currently pending interrupt bits of the IP passed from the caller into "ClearMask". </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">ClearMask</td><td>is the bit pattern for pending interrupts wanted to be cleared.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#gaf4ee25f8cd866c3c4c79bd9f1a784a7c">XAXIPCIE_ID_OFFSET</a>, <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>, and <a class="el" href="group__axipcie__v3__0.html#gaf3312e39c24adeb6a06a7408a68a1e80">XAxiPcie_WriteReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__ep__cdma__example_8c.html#a0305d38f6ee9ba0d3e2e545b96201ce3">PCIeEndPointInitialize()</a>, and <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga225811fdbd9b22b8208a83ca4d3818ce">&#9670;&nbsp;</a></span>XAxiPcie_ClearRootPortErrFIFOMsg()</h2>

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      <table class="memname">
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          <td class="memname">void XAxiPcie_ClearRootPortErrFIFOMsg </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Clear Root Port Error FIFO Message. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the PCIe component to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a9cf8eebd3200725c2102ea9c1a5aea28">XAxiPcie_Config::IncludeRootComplex</a>, and <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga4b043d41a5668f97f83518327023ea0d">&#9670;&nbsp;</a></span>XAxiPcie_ClearRootPortIntFIFOReg()</h2>

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      <table class="memname">
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          <td class="memname">void XAxiPcie_ClearRootPortIntFIFOReg </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Clear Root Port FIFO Interrupt message Register 1 &amp; 2. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the PCIe component to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex.Clearing any one Interrupt FIFO register clears both registers. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a9cf8eebd3200725c2102ea9c1a5aea28">XAxiPcie_Config::IncludeRootComplex</a>, and <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaace3ba2f6c70cd207c9c65d92c634ee8">&#9670;&nbsp;</a></span>XAxiPcie_DisableGlobalInterrupt()</h2>

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      <table class="memname">
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          <td class="memname">void XAxiPcie_DisableGlobalInterrupt </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Disable the Global Interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This bit is in the Bridge Status and Control Register. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#ga6a80436f1d395be5d4963d3f9d09f49c">XAXIPCIE_BSC_GI_MASK</a>, <a class="el" href="group__axipcie__v3__0.html#ga92e6aa96f3a966ac3ac8b8b00bb770e6">XAXIPCIE_BSC_GI_SHIFT</a>, <a class="el" href="group__axipcie__v3__0.html#ga10e385edef3931106642fcf07d5a5fec">XAXIPCIE_BSC_OFFSET</a>, <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>, and <a class="el" href="group__axipcie__v3__0.html#gaf3312e39c24adeb6a06a7408a68a1e80">XAxiPcie_WriteReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gae238cf115bd039e0f7228e385c893aad">&#9670;&nbsp;</a></span>XAxiPcie_DisableInterrupts()</h2>

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<div class="memproto">
      <table class="memname">
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          <td class="memname">void XAxiPcie_DisableInterrupts </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>DisableMask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Disable the IP interrupt bits passed into "DisableMask". </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DisableMask</td><td>is the bit pattern for interrupts wanted to be disabled.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>If an interrupt is already disabled before calling this function, it will stay disabled regardless of the value of "DisableMask" passed from the caller. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#gad798e4bbf2fc4fe5135dfa56fac31399">XAXIPCIE_IM_OFFSET</a>, <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>, and <a class="el" href="group__axipcie__v3__0.html#gaf3312e39c24adeb6a06a7408a68a1e80">XAxiPcie_WriteReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__ep__cdma__example_8c.html#a0305d38f6ee9ba0d3e2e545b96201ce3">PCIeEndPointInitialize()</a>, <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>, and <a class="el" href="group__axipcie__v3__0.html#ga6eaa13c68af6eb2ca12ae556f9e0769b">XAxiPcie_CfgInitialize()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga062809d176f81251886d5372c0714f7a">&#9670;&nbsp;</a></span>XAxiPcie_EnableGlobalInterrupt()</h2>

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      <table class="memname">
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          <td class="memname">void XAxiPcie_EnableGlobalInterrupt </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Enable the Global Interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This bit is in the Bridge Status and Control Register. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#ga6a80436f1d395be5d4963d3f9d09f49c">XAXIPCIE_BSC_GI_MASK</a>, <a class="el" href="group__axipcie__v3__0.html#ga92e6aa96f3a966ac3ac8b8b00bb770e6">XAXIPCIE_BSC_GI_SHIFT</a>, <a class="el" href="group__axipcie__v3__0.html#ga10e385edef3931106642fcf07d5a5fec">XAXIPCIE_BSC_OFFSET</a>, <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>, and <a class="el" href="group__axipcie__v3__0.html#gaf3312e39c24adeb6a06a7408a68a1e80">XAxiPcie_WriteReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga22a95261655e78a944d1a2462031da57">&#9670;&nbsp;</a></span>XAxiPcie_EnableInterrupts()</h2>

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<div class="memproto">
      <table class="memname">
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          <td class="memname">void XAxiPcie_EnableInterrupts </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>EnableMask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Enable the IP interrupt bits passed into "EnableMask". </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">EnableMask</td><td>is the bit pattern for interrupts wanted to be enabled.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>If an interrupt is already enabled before calling this function, it will stay enabled regardless of the value of "EnableMask" passed from the caller. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#gad798e4bbf2fc4fe5135dfa56fac31399">XAXIPCIE_IM_OFFSET</a>, <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>, and <a class="el" href="group__axipcie__v3__0.html#gaf3312e39c24adeb6a06a7408a68a1e80">XAxiPcie_WriteReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga75ca6a068024666c0199ea90d3ce4276">&#9670;&nbsp;</a></span>XAxiPcie_GetBridgeInfo()</h2>

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      <table class="memname">
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          <td class="memname">void XAxiPcie_GetBridgeInfo </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Gen2Ptr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>RootPortPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>ECAMSizePtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>This API Reads the Bridge info register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">Gen2Ptr</td><td>is a pointer to a variable indicating whether underlying PCIe block support PCIe Gen2 Speed. </td></tr>
    <tr><td class="paramname">RootPortPtr</td><td>is a pointer to a variable indication whether underlying PCIe block is root port. </td></tr>
    <tr><td class="paramname">ECAMSizePtr</td><td>is a pointer to a variable where it indicates ECAM size. Value is between 1 to 8. Total address bits dedicated to ECAM is 20 + ECAM size.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#ga2d99e62d5248da57465cd526eaf9cb01">XAXIPCIE_BI_ECAM_SIZE_MASK</a>, <a class="el" href="group__axipcie__v3__0.html#ga6e5ee78d2b39fa90a87fea37ed49d35a">XAXIPCIE_BI_ECAM_SIZE_SHIFT</a>, <a class="el" href="group__axipcie__v3__0.html#ga5c3e13956927d814f89b16d58bc87b71">XAXIPCIE_BI_GEN2_MASK</a>, <a class="el" href="group__axipcie__v3__0.html#ga9f8bb352119692caff9e7851fe534498">XAXIPCIE_BI_OFFSET</a>, <a class="el" href="group__axipcie__v3__0.html#gab624cf074fe8d343c15a086782e1150c">XAXIPCIE_BI_RP_MASK</a>, <a class="el" href="group__axipcie__v3__0.html#gae20709cf0062b87ed8689af2e8ee0a0a">XAXIPCIE_BI_RP_SHIFT</a>, and <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gae118e9d7fd6b78ca0b8d4fd6694f9808">&#9670;&nbsp;</a></span>XAxiPcie_GetEnabledInterrupts()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAxiPcie_GetEnabledInterrupts </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>EnabledMaskPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Get the currently enabled interrupt bits of the IP and pass them back to the caller into "EnabledMask". </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">EnabledMaskPtr</td><td>is a pointer to a variable where the driver will pass back the enabled interrupt bits after reading them from IP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#gad798e4bbf2fc4fe5135dfa56fac31399">XAXIPCIE_IM_OFFSET</a>, and <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__ep__cdma__example_8c.html#a0305d38f6ee9ba0d3e2e545b96201ce3">PCIeEndPointInitialize()</a>, and <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga19d8a1973231160bdd518b1c62bda3d4">&#9670;&nbsp;</a></span>XAxiPcie_GetLocalBusBar2PcieBar()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAxiPcie_GetLocalBusBar2PcieBar </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>BarNumber</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie___bar_addr.html">XAxiPcie_BarAddr</a> *&#160;</td>
          <td class="paramname"><em>BarAddrPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Read PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">BarNumber</td><td>is AXI bar number (0 - 5) passed by caller. </td></tr>
    <tr><td class="paramname">BarAddrPtr</td><td>is a pointer to a variable where the driver will . pass back translation vector.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a57ad5737694668f53134af341ccf9428">XAxiPcie_Config::IncludeBarOffsetReg</a>, <a class="el" href="struct_x_axi_pcie___bar_addr.html#a391e43cdec653f3299116b3a14f127af">XAxiPcie_BarAddr::LowerAddr</a>, <a class="el" href="struct_x_axi_pcie___bar_addr.html#a3a5ba3ab465659a83a0a76b63fcb104a">XAxiPcie_BarAddr::UpperAddr</a>, <a class="el" href="group__axipcie__v3__0.html#gaa01b566fdaa57bf0696c4a4445053158">XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET</a>, <a class="el" href="group__axipcie__v3__0.html#gace702755df9d438185fdb96c5e63cc0e">XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET</a>, and <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaec39c65db1aeac38798a250a25298208">&#9670;&nbsp;</a></span>XAxiPcie_GetPendingInterrupts()</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAxiPcie_GetPendingInterrupts </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>PendingMaskPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Get the currently pending interrupt bits of the IP and pass them back to the caller into "PendingMask". </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">PendingMaskPtr</td><td>is a pointer to a variable where the driver will pass back the pending interrupt bits after reading them from IP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#gaf4ee25f8cd866c3c4c79bd9f1a784a7c">XAXIPCIE_ID_OFFSET</a>, and <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__ep__cdma__example_8c.html#a0305d38f6ee9ba0d3e2e545b96201ce3">PCIeEndPointInitialize()</a>, and <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga372301905fec6833c06320fb45261cd7">&#9670;&nbsp;</a></span>XAxiPcie_GetPhyStatusCtrl()</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAxiPcie_GetPhyStatusCtrl </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>PhyState</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>This API is used to read the Phy Status/Control Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">PhyState</td><td>is a pointer to a variable where the driver will pass back Current physical status.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#ga84f89f155288e2a5de41a09bdf5d8672">XAXIPCIE_PHYSC_OFFSET</a>, and <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga77063428b5641d07910419770813c148">&#9670;&nbsp;</a></span>XAxiPcie_GetRequesterId()</h2>

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      <table class="memname">
        <tr>
          <td class="memname">void XAxiPcie_GetRequesterId </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>BusNumPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>DevNumPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>FunNumPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>PortNumPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Read the Bus Location register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">BusNumPtr</td><td>is a pointer to a variable where the driver will pass back the bus number of requester ID assigned to IP. </td></tr>
    <tr><td class="paramname">DevNumPtr</td><td>is a pointer to a variable where the driver will pass back the device number of requester ID assigned to IP. </td></tr>
    <tr><td class="paramname">FunNumPtr</td><td>is a pointer to a variable where the driver will pass back the function number of requester ID assigned to IP. </td></tr>
    <tr><td class="paramname">PortNumPtr</td><td>is a pointer to a variable where the driver will pass back the Port number of requester ID assigned to IP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#gaf8a11f087363d5ff57409bf45a597851">XAXIPCIE_BL_BUS_MASK</a>, <a class="el" href="group__axipcie__v3__0.html#gadc5afc68e0ece36131a9636a467ab327">XAXIPCIE_BL_BUS_SHIFT</a>, <a class="el" href="group__axipcie__v3__0.html#ga21a35da125896346b1a3219fe2dfcc93">XAXIPCIE_BL_DEV_MASK</a>, <a class="el" href="group__axipcie__v3__0.html#gaf0d3ce908be6f6c89a7212ddc42ba192">XAXIPCIE_BL_DEV_SHIFT</a>, <a class="el" href="group__axipcie__v3__0.html#ga269fecd1e2d8010e7b84e1339a5b2b94">XAXIPCIE_BL_FUNC_MASK</a>, <a class="el" href="group__axipcie__v3__0.html#gae8a758a6bb3b73be59a403a53ef97881">XAXIPCIE_BL_OFFSET</a>, <a class="el" href="group__axipcie__v3__0.html#gae40bca0b490429edd0c59df2f04dd595">XAXIPCIE_BL_PORT_MASK</a>, <a class="el" href="group__axipcie__v3__0.html#ga7ef6bab98d1eba6156f808f92e39d7f2">XAXIPCIE_BL_PORT_SHIFT</a>, and <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__rc__enumerate__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga32604cb99f7d35107ee59ff121e0024d">&#9670;&nbsp;</a></span>XAxiPcie_GetRootPortErrFIFOMsg()</h2>

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<div class="memproto">
      <table class="memname">
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          <td class="memname">void XAxiPcie_GetRootPortErrFIFOMsg </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16 *&#160;</td>
          <td class="paramname"><em>ReqIdPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>ErrType</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>ErrValid</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Read Root Port Error FIFO Message. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the PCIe component to operate on. </td></tr>
    <tr><td class="paramname">ReqIdPtr</td><td>is a variable where the driver will pass back the requester Id of error message. </td></tr>
    <tr><td class="paramname">ErrType</td><td>is a variable where the driver will pass back the type of error message </td></tr>
    <tr><td class="paramname">ErrValid</td><td>is a variable where the driver will pass back the status of read operation of error message.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a9cf8eebd3200725c2102ea9c1a5aea28">XAxiPcie_Config::IncludeRootComplex</a>, and <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga8b13520d9f4472bc16cfa5a6266f6795">&#9670;&nbsp;</a></span>XAxiPcie_GetRootPortIntFIFOReg()</h2>

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<div class="memproto">
      <table class="memname">
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          <td class="memname">int XAxiPcie_GetRootPortIntFIFOReg </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16 *&#160;</td>
          <td class="paramname"><em>ReqIdPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16 *&#160;</td>
          <td class="paramname"><em>MsiAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsiInt</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>IntValid</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16 *&#160;</td>
          <td class="paramname"><em>MsiMsgData</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Read Root Port Interrupt FIFO message Register 1 &amp; 2. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the PCIe component to operate on. </td></tr>
    <tr><td class="paramname">ReqIdPtr</td><td>is a variable where the driver will pass back the requester Id of error message. </td></tr>
    <tr><td class="paramname">MsiAddr</td><td>is a variable where the driver will pass back the MSI address for which interrupt message recieved. </td></tr>
    <tr><td class="paramname">MsiInt</td><td>is a variable where the driver will pass back the type of interrupt message recieved (MSI/INTx). </td></tr>
    <tr><td class="paramname">IntValid</td><td>is a variable where the driver will pass back the status of read operation of interrupt message. </td></tr>
    <tr><td class="paramname">MsiMsgData</td><td>is a variable where the driver will pass back the MSI data recieved.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>MsiMsgData if MSI interrupt is observed or 0 if there is no MSI interrupt.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a9cf8eebd3200725c2102ea9c1a5aea28">XAxiPcie_Config::IncludeRootComplex</a>, and <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0899628f4ecfb6d3b05671933c375ae5">&#9670;&nbsp;</a></span>XAxiPcie_GetRootPortStatusCtrl()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAxiPcie_GetRootPortStatusCtrl </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>StatusPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Read Root Port Status/Control Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the PCIe component to operate on. </td></tr>
    <tr><td class="paramname">StatusPtr</td><td>is a pointer to a variable where the driver will pass back the root port status.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a9cf8eebd3200725c2102ea9c1a5aea28">XAxiPcie_Config::IncludeRootComplex</a>, and <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga745d2811e366fbe0e5499cfef90adbcc">&#9670;&nbsp;</a></span>XAxiPcie_GetVsecCapability()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAxiPcie_GetVsecCapability </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>VsecNum</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16 *&#160;</td>
          <td class="paramname"><em>VsecIdPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>VersionPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16 *&#160;</td>
          <td class="paramname"><em>NextCapPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>This API is used to read the VSEC Capability Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">VsecNum</td><td>is a VSEC register number as there are two registers. Possible values are.<ul>
<li>XAXIPCIE_VSEC1 (0)</li>
<li>XAXIPCIE_VSEC2 (1) </li>
</ul>
</td></tr>
    <tr><td class="paramname">VsecIdPtr</td><td>is a pointer to a variable where the driver will pass back the Vendor Specific Enhanced Capability ID. </td></tr>
    <tr><td class="paramname">VersionPtr</td><td>is a pointer to a variable where the driver will . pass back the Version of VSEC. </td></tr>
    <tr><td class="paramname">NextCapPtr</td><td>is a pointer to a variable where the driver will pass back the Next Capability offset.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>, and <a class="el" href="group__axipcie__v3__0.html#gaf01ed785ab64d6c124437532ece335ce">XAXIPCIE_VSECC_OFFSET</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaa26f5255cb42e55351c7cb802f71d56c">&#9670;&nbsp;</a></span>XAxiPcie_GetVsecHeader()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAxiPcie_GetVsecHeader </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>VsecNum</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16 *&#160;</td>
          <td class="paramname"><em>VsecIdPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>RevisionPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16 *&#160;</td>
          <td class="paramname"><em>LengthPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>This API is used to read the VSEC Header Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">VsecNum</td><td>is a VSEC register number as there are two registers. Possible values are.<ul>
<li>XAXIPCIE_VSEC1 (0)</li>
<li>XAXIPCIE_VSEC2 (1) </li>
</ul>
</td></tr>
    <tr><td class="paramname">VsecIdPtr</td><td>is a pointer to a variable where the driver will pass back the VSEC header structure Id. </td></tr>
    <tr><td class="paramname">RevisionPtr</td><td>is a pointer to a variable where the driver will pass back the Revision of VSEC capability Structure. </td></tr>
    <tr><td class="paramname">LengthPtr</td><td>is a pointer to a variable where the driver will pass . back the length of the VSEC capability structure.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>, and <a class="el" href="group__axipcie__v3__0.html#gab99ecd675b55df50a385fc7b429d38e4">XAXIPCIE_VSECH_OFFSET</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga911e4cd0c119271f6c01c9b1ac827df1">&#9670;&nbsp;</a></span>XAxiPcie_LookupConfig()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><a class="el" href="struct_x_axi_pcie___config.html">XAxiPcie_Config</a>* XAxiPcie_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Lookup the device configuration based on the unique device ID. </p>
<p>The table ConfigTable contains the configuration info for each device in the system.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the device identifier to lookup.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li><a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> configuration structure pointer if DeviceID is found.</li>
<li>NULL if DeviceID is not found.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p class="reference">Referenced by <a class="el" href="xaxipcie__ep__cdma__example_8c.html#a0305d38f6ee9ba0d3e2e545b96201ce3">PCIeEndPointInitialize()</a>, and <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gad9494095b9350f455af9e7da5375d522">&#9670;&nbsp;</a></span>XAxiPcie_ReadLocalConfigSpace()</h2>

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<div class="memproto">
      <table class="memname">
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          <td class="memname">void XAxiPcie_ReadLocalConfigSpace </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>Offset</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>DataPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Read 32-bit value from one of this IP own configuration space. </p>
<p>Location is identified by its offset from the beginning of the configuration space.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">Offset</td><td>from beginning of IP own configuration space. </td></tr>
    <tr><td class="paramname">DataPtr</td><td>is a pointer to a variable where the driver will pass back the value read from the specified location.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>, <a class="el" href="group__axipcie__v3__0.html#ga7cecef23e8a28935226e7dc9815390c0">XAXIPCIE_PCIE_CORE_OFFSET</a>, and <a class="el" href="group__axipcie__v3__0.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__ep__cdma__example_8c.html#a0305d38f6ee9ba0d3e2e545b96201ce3">PCIeEndPointInitialize()</a>, and <a class="el" href="xaxipcie__rc__enumerate__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gae4aafc6b1766352ed5347e40762f0649">&#9670;&nbsp;</a></span>XAxiPcie_ReadRemoteConfigSpace()</h2>

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<div class="memproto">
      <table class="memname">
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          <td class="memname">void XAxiPcie_ReadRemoteConfigSpace </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bus</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Device</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Function</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>Offset</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>DataPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Read 32-bit value from external PCIe Function's configuration space. </p>
<p>External PCIe function is identified by its Requester ID (Bus#, Device#, Function#). Location is identified by its offset from the begginning of the configuration space.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the PCIe component to operate on. </td></tr>
    <tr><td class="paramname">Bus</td><td>is the external PCIe function's Bus number. </td></tr>
    <tr><td class="paramname">Device</td><td>is the external PCIe function's Device number. </td></tr>
    <tr><td class="paramname">Function</td><td>is the external PCIe function's Function number. </td></tr>
    <tr><td class="paramname">Offset</td><td>from beggininng of PCIe function's configuration space. </td></tr>
    <tr><td class="paramname">DataPtr</td><td>is a pointer to a variable where the driver will pass back the value read from the specified location.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex. The XAxiPcie_ReadLocalConfigSpace API should be used for reading the local config space. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a9cf8eebd3200725c2102ea9c1a5aea28">XAxiPcie_Config::IncludeRootComplex</a>, and <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga51ee29d03fbefc82b9208f46a12d5a06">&#9670;&nbsp;</a></span>XAxiPcie_SetLocalBusBar2PcieBar()</h2>

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      <table class="memname">
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          <td class="memname">void XAxiPcie_SetLocalBusBar2PcieBar </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>BarNumber</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie___bar_addr.html">XAxiPcie_BarAddr</a> *&#160;</td>
          <td class="paramname"><em>BarAddrPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Write PCIe address translation vector that corresponds to one of AXI local bus bars passed by the caller. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_axi_pcie.html" title="The XAxiPcie driver instance data. ">XAxiPcie</a> instance to operate on. </td></tr>
    <tr><td class="paramname">BarNumber</td><td>is AXI bar number (0 - 5) passed by caller. </td></tr>
    <tr><td class="paramname">BarAddrPtr</td><td>is a pointer to a variable where the driver will pass back translation vector.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie___config.html#a98bdcba67cfa7c75179ae1b0b7b6415f">XAxiPcie_Config::BaseAddress</a>, <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a57ad5737694668f53134af341ccf9428">XAxiPcie_Config::IncludeBarOffsetReg</a>, <a class="el" href="struct_x_axi_pcie___bar_addr.html#a391e43cdec653f3299116b3a14f127af">XAxiPcie_BarAddr::LowerAddr</a>, <a class="el" href="struct_x_axi_pcie___bar_addr.html#a3a5ba3ab465659a83a0a76b63fcb104a">XAxiPcie_BarAddr::UpperAddr</a>, <a class="el" href="group__axipcie__v3__0.html#gaa01b566fdaa57bf0696c4a4445053158">XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET</a>, <a class="el" href="group__axipcie__v3__0.html#gace702755df9d438185fdb96c5e63cc0e">XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET</a>, and <a class="el" href="group__axipcie__v3__0.html#gaf3312e39c24adeb6a06a7408a68a1e80">XAxiPcie_WriteReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="xaxipcie__rc__cdma__example_8c.html#ae4d64f629bd35e874ac76b2e7159b73f">PcieInitRootComplex()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0ce4f790929f629f225c2ef2fbcc2647">&#9670;&nbsp;</a></span>XAxiPcie_SetRootPortMSIBase()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">int XAxiPcie_SetRootPortMSIBase </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned long long&#160;</td>
          <td class="paramname"><em>MsiBase</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Write MSI Base Address to Root Port MSI Base Address Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the PCIe component to operate on. </td></tr>
    <tr><td class="paramname">MsiBase</td><td>is 64 bit base address for MSI.This address should be 4kB aligned always.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XST_SUCCESS if success or XST_FAILURE if failure .</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a9cf8eebd3200725c2102ea9c1a5aea28">XAxiPcie_Config::IncludeRootComplex</a>, and <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2860cd7b0180a99fb324c085fc8fa746">&#9670;&nbsp;</a></span>XAxiPcie_SetRootPortStatusCtrl()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAxiPcie_SetRootPortStatusCtrl </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>StatusData</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Write Value in Root Port Status/Control Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the PCIe component to operate on. </td></tr>
    <tr><td class="paramname">StatusData</td><td>is data to set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a9cf8eebd3200725c2102ea9c1a5aea28">XAxiPcie_Config::IncludeRootComplex</a>, and <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gafbdf9a7e71effb96353079d1c177888b">&#9670;&nbsp;</a></span>XAxiPcie_WriteLocalConfigSpace()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAxiPcie_WriteLocalConfigSpace </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>Offset</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Write 32-bit value to one of this IP own configuration space. </p>
<p>Location is identified by its offset from the begginning of the configuration space.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the PCIe component to operate on. </td></tr>
    <tr><td class="paramname">Offset</td><td>from beggininng of IP own configuration space. </td></tr>
    <tr><td class="paramname">Data</td><td>to be written to the specified location.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a9cf8eebd3200725c2102ea9c1a5aea28">XAxiPcie_Config::IncludeRootComplex</a>, and <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gadb4d67df95f1c7b0010e370312283f22">&#9670;&nbsp;</a></span>XAxiPcie_WriteRemoteConfigSpace()</h2>

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<div class="memproto">
      <table class="memname">
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          <td class="memname">void XAxiPcie_WriteRemoteConfigSpace </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bus</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Device</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Function</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>Offset</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxipcie_8h.html">xaxipcie.h</a>&gt;</code></p>

<p>Write 32-bit value to external PCIe function's configuration space. </p>
<p>External PCIe function is identified by its Requester ID (Bus#, Device#, Function#). Location is identified by its offset from the begginning of the configuration space.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the PCIe component to operate on. </td></tr>
    <tr><td class="paramname">Bus</td><td>is the external PCIe function's Bus number. </td></tr>
    <tr><td class="paramname">Device</td><td>is the external PCIe function's Device number. </td></tr>
    <tr><td class="paramname">Function</td><td>is the external PCIe function's Function number. </td></tr>
    <tr><td class="paramname">Offset</td><td>from beggininng of PCIe function's configuration space. </td></tr>
    <tr><td class="paramname">Data</td><td>to be written to the specified location.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is valid only when IP is configured as a root complex. The XAxiPcie_WriteLocalConfigSpace should be used for writing to local config space. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_pcie.html#ab87e6544d15c1c11d8aaba5021606363">XAxiPcie::Config</a>, <a class="el" href="struct_x_axi_pcie___config.html#a9cf8eebd3200725c2102ea9c1a5aea28">XAxiPcie_Config::IncludeRootComplex</a>, and <a class="el" href="struct_x_axi_pcie.html#aa3d7812e2f5b430c9a551f735b8e0c69">XAxiPcie::IsReady</a>.</p>

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